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toshiba original cmos 32-bit microcontroller tlcs-900/h1 series TMP92FD54AIFG tentative semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the section, ?points of note and restrictions?.
tmp92fd54ai 2009-12-26 92fd54ai-1 tentative cmos 32-bit micro-controller TMP92FD54AIFG 1. device outline and characteristics the tmp92fd54ai is a high-performance 32-bi t microcontroller incorp orating a toshiba- proprietary cpu, the tlcs-900/h1 core. the tmp 92fd54ai is developed fo r various automotive equipments which require high-speed data processing. housed in a 100-pin mini-flat package, the tm p92fd54ai is best suited for high-density implementation of user systems. the characteristics of the tmp92fd54ai are listed below: (1) toshiba-proprietary high-speed 32-bit cpu (tlcs-900/h1 cpu) fully-compatible with the instruction codes of the tlcs-900, tlcs-900/l, elcs-900/l1, tlcs-900/h and tlcs-900/h2 16 mbytes of linear address space general-purpose registers and register banks micro dma: 8 channels (250 ns/4 bytes at fc = 20 mhz) minimum instruction execution time: 50 ns (at fc = 20 mhz) internal data bus: 32-bit wide (2) internal memory internal ram : 32 kbytes internal rom : 512-kbyte flash eeprom 3-kbyte masked rom (for single boot mode) (3) external memory expansion expandable up to 16-mbyte (for code and data) external data bus: 8-bit wide (the upper addr ess bus is not available when the built-in i/os are selected.) (4) memory controller (memc) chip select output: 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (ppg) output mode (4 channels) 8-bit pulse width modulation (pwm) output mode (4 channels) (6) 16-bit timer : 2 channels 16-bit interval timer mode (2 channels) 16-bit event counter mode (2 channels) 16-bit programmable pulse generation (ppg) output mode (2 channels) frequency measurement mode pulse width measurement mode time difference measurement mode (7) general-purpose serial interface (sio) : 2 channels i/o interface mode universal asynchronous receiver transmitter (uart) mode (8) serial expansion interface (sei) : 1 channel (9) baud rate: 4 m/2 m/500 k bps at fc = 20 mhz
tmp92fd54ai 2009-12-26 92fd54ai-2 tentative (10) serial bus interface (sbi): 3 channels clock-synchronous 8-bit serial interface mode i 2 c bus mode (11) can controller : 1 channel supports can version 2.0b. 16 mailboxes (12) 10-bit a/d converter (adc) : 12 channels a/d conversion time: 8 sec (at fc = 20 mhz) total tolerance: 3 lsb (excluding quantization error) scan mode for all 12 channels (13) watch dog timer (wdt) (14) timer for real-time clock (rtc) can operate with low-frequency oscillator only. (15) interrupt controller (intc) : 60 interrupt sources 9 interrupts from cpu (software interrupts and undefined instruction interrupt) 42 internal interrupt vectors 9 external interrupt vectors (int0 to int7, nmi ) (16) i/o port : 68 pins (including multi-function pins) (17) standby mode four modes: idle3, idle2, idle1 and stop stop mode can be released by 9 external inputs. (17) internal voltage detection flag (ramstb) (18) power supply voltage v cc5 = 4.5 v to 5.25 v v cc3 = 3.3 v (connect regout (built-in vo ltage regulator output) to dvcc3.) (19) operating temperature: -40 to 85 degree c (0 to 70 de gree c when the flash memo ry is being rewritten.) (20) package : lqfp100-p-1414-0.50h
tmp92fd54ai 2009-12-26 92fd54ai-3 tentative figure 1.1 tmp92fd54ai block diagram dvcc3 [3] pm0( ss /a8) pm1(mosi/a9) pm2(miso/a10) pm3(seclk/a11) pn0(sck0) pn1(so0/sda0) pn2(si0/scl0) pn3(sck1/a12) pn4(so1/sda1/a13) pn5(si1/scl1/a14) p00~p07(d0~d7) p40~p47(a0~a7) p70 ( rd ) p71 ( wr ) p73 ( cs ) p74 p75 ( wait ) dvss [6] dvcc5 [5] regen port 0 port 4 interrupt controller serial bus i/f channel 0 serial bus i/f channel 1 serial expansion i/f int0 port 7 32kb ram 512kb flash e 2 prom serial i/o channel 0 serial i/o channel 1 10-bit 12-ch a/d converter 32 bits xsp xiz xiy xix xhl xde xbc xwa ix iy iz sp l h e d c b a w f sr p c 900/h1 cpu watch-dog timer (wdt) real time clock (rtc) (to7/int4)pc5 8-bit timer (timer0) 8-bit timer (timer1) 8-bit timer (timer2) 8-bit timer (timer3) 8-bit timer (timer4) 8-bit timer (timer5) 8-bit timer (timer6) 8-bit timer (timer7) (ti4/int3)pc3 (to3/int2)pc2 (to5)pc4 (ti0/int1)pc0 (to1)pc1 can controller (tx)pf6 (rx)pf7 vrefl vrefh advss advcc pg0~pg7 (an0~an7) pl0~pl3 (an8~an11) regout xt1 xt2 x1 x2 serial bus i/f channel 2 pm4(sck2) pn6(so2/sda2/a15) p72(si2/scl2) nmi a m0 a m1 test0 test1 reset (sc lk 0/ c t s0 ) pf2 (rxd0)pf1 (txd0)pf0 (sc lk1 / c t s 1 ) pf 5 (rxd1)pf4 (txd1)pf3 (ti9/wuint1/int6/a17)pd1 (ti8/wuint0/int5/a16)pd0 (to8/wuint2/a18)pd2 (to9/wuint3/a19)pd3 (tia/wuint4/int7/a20)pd4 (tib/wuint5/a21)pd5 (toa/wuint6/a22)pd6 (tob/wuint7/a23)pd7 16-bit timer (timer8) 16-bit timer (timera) osc rtc regulator clk connect 3-kb mask rom (for flash single boot mode)
tmp92fd54ai 2009-12-26 92fd54ai-4 tentative 2. pin assignment and functions 2.1 pin assignment figure 2.1 pin assignment dvcc5 x1 dvss x2 test1 xt1 xt2 dvcc3 pn6/so2/sda2/a15 pn5/si1/scl1/a14 pn4/so1/sda1/a13 pn3/sck1/a12 dvss pn2/si0/scl0 dvcc5 pn1/so0/sda0 pn0/sck0 pc0/ti0/int1 pc1/to1 pc2/to3/int2 pc3/ti4/int3 pc4/to5 pc5/to7/int4 regen dvss pl3/an11 pl2/an10 pl1/an9 pl0/an8 pg7/an7 pg6/an6 pg5/an5 pg4/an4 pg3/an3 pg2/an2 pg1/an1 pg0/an0 dvss p75/wait dvcc3 p74 p73/cs p72/si2/scl2 p71/wr p70/rd am0 reset am1 clk test0 TMP92FD54AIFG (lqfp100-p-1414-0.50h) 14 14 1.4 top view 01 05 10 15 20 25 75 70 65 60 55 51 50 45 40 35 30 26 076 080 085 090 095 d6/p06 d7/p07 a0/p40 a1/p41 a2/p42 a3/p43 a4/p44 a5/p45 a6/p46 a7/p47 dvcc3 int0 dvss nmi dvcc5 a16/wuint0/int5/ti8/pd0 a17/wuint1/int6/ti9/pd1 a18/wuint2/to8/pd2 a19/wuint3/to9/pd3 a20/wuint4/int7/tia/pd4 a21/wuint5/tib/pd5 a22/wuint6/toa/pd6 a23/wuint7/tob/pd7 regout dvcc5 100 advss advcc vrefl vrefh rx/pf7 tx/pf6 cts1/sclk1/pf5 rxd1/pf4 txd1/pf3 cts0/sclk0/pf2 rxd0/pf1 txd0/pf0 dvss pm4/sck2 dvcc5 a8/ss/pm0 a9/mosi/pm1 a10/miso/pm2 a11/seclk/pm3 d0/p00 d1/p01 d2/p02 d3/p03 d4/p04 d5/p05
tmp92fd54ai 2009-12-26 92fd54ai-5 tentative 2.2 pin names and functions the names and functions of the input/output pins are described in tables 2.2.1 to 2.2.4. table 2.2.1 input/output pins (1/4) pin name pin number number of pins in/out function (cmos) p00 to p07 d0 to d7 20 to 27 8 (ttl) in/out in/out port 0: i/o port. input or output specifiable in units of bits. data: data bus 0 to 7. p40 to p47 a0 to a7 28 to 35 8 in/out out port4: i/o port. input or output specifiable in units of bits. address: address bus 0 to 7. p70 rd 81 1 in/out out port70: i/o port. read: outputs strobe signal to read external memory. p71 wr 82 1 in/out out port 71: i/o port. write: output strobe signal to write external memory. p72 si2 scl2 83 1 in/out port 72: i/o port. sbi channel 2: input data at sio mode sbi channel 2: clock input/output at i2c mode p73 cs 84 1 in/out out port 73: i/o port. chip select: outputs ?low? if address is within specified address area. p74 85 1 in/out port 74: i/o port. p75 wait 87 1 in/out in port 75: i/o port. wait: signal used to request cpu bus wait. pc0 ti0 int1 58 1 in/out in in port c0: i/o port. timer input 0: input pin for timer 0. interrupt request pin 1: risi ng-edge interrupt request pin. pc1 to1 57 1 in/out out port c1: i/o port. timer output 1: output pin for timer 1. pc2 to3 int2 56 1 in/out out in port c2: i/o port. timer output 3: output pin for timer 3. interrupt request pin 2: risi ng-edge interrupt request pin. pc3 ti4 int3 55 1 in/out in in port c3: i/o port. timer input 4: input pin for timer 4. interrupt request pin 3: risi ng-edge interrupt request pin. pc4 to5 54 1 in/out out port c4: i/o port. timer output 5: output pin for timer 5. pc5 to7 int4 53 1 in/out out in port c5: i/o port. timer output 7: output pin for timer 7. interrupt request pin 4: risi ng-edge interrupt request pin. pd0 ti8 int5 a16 wuint0 41 1 in/out in in out in port d0: i/o port. timer input 8: input pin for timer 8. interrupt request pin 5: interrupt request pin with programmable rising/falling edge. address: address bus 16. wake up input 0: wake up request pin with programmable rising, falling or both falling and rising edge. pd1 ti9 int6 a17 wuint1 42 1 in/out in in out in port d1: i/o port. timer input 9: input pin for timer 9. interrupt request pin 6: rising- edge interrupt request pin. address: address bus 17. wake up input 1: wake up request pin with programmable rising, falling or both falling and rising edge. pd2 to8 a18 wuint2 43 1 in/out out out in port d2: i/o port. timer output 8: output pin for timer 8 address: address bus 18. wake up input 2: wake up request pin with programmable rising, falling or both falling and rising edge. wuint2 wuint0 wuint1 int6 int1 int2 int3 int4 int5
tmp92fd54ai 2009-12-26 92fd54ai-6 tentative table 2.2.2 input/output pins (2/4) pin name pin number number of pins in/out function pd3 to9 a19 wuint3 44 1 in/out out out in port d3: i/o port. timer output 9: output pin for timer 9 address: address bus 19. wake up input 3: wake up request pin with programmable rising, falling or both falling and rising edge. pd4 tia int7 a20 wuint4 45 1 in/out in in out in port d4: i/o port. timer input a: input pin for timer a interrupt request pin 7: interrupt reques t pin with programmable rising/falling edge. address: address bus 20. wake up input 4: wake up request pin with programmable rising, falling or both falling and rising edge. pd5 tib a21 wuint5 46 1 in/out in out in port d5: i/o port. timer input b: input pin for timer b. address: address bus 21. wake up input 5: wake up request pin with programmable rising, falling or both falling and rising edge. pd6 toa a22 wuint6 47 1 in/out out out in port d6: i/o port. timer output a: output pin for timer a. address: address bus 22. wake up input 6: wake up request pin with programmable rising, falling or both falling and rising edge. pd7 tob a23 wuint7 48 1 in/out out out in port d7: i/o port. timer output b: output pin for timer b. address: address bus 23. wake up input 7: wake up request pin with programmable rising, falling or both falling and rising edge. pf0 txd0 12 1 in/out out port f0: i/o port. serial interface channel 0: transmission data. pf1 rxd0 11 1 in/out in port f1: i/o port. serial interface channel 0: receive data. pf2 sclk0 cts0 10 1 in/out in/out in port f2: i/o port. serial interface channel 0: clock input/output. serial interface channel 0: data ready to send. (clear-to-send) pf3 txd1 9 1 in/out out port f3: i/o port. serial interface channel 1: transmission data. pf4 rxd1 8 1 in/out in port f4: i/o port. serial interface channel 1: receive data. pf5 sclk1 cts1 7 1 in/out in/out in port f5: i/o port. serial interface channel 1: clock input/output. serial interface channel 1: data ready to send. (clear-to-send) pf6 tx 6 1 in/out out port f6: i/o port. can: transmission data. pf7 rx 5 1 in/out in port f7: i/o port. can: receive data. pg0 to pg7 an0 to an7 89 to 96 8 in in port g: input-only port. analog input 0 to 7: ad converter input pins. pl0 to pl3 an8 to an11 97 to 100 4 in in port l0 to l3: input-only port. analog input 8 to 11: ad converter input pins. pm0 ss a8 16 1 in/out in out port m0: i/o port. sei: slave select input. address: address bus 8. pm1 mosi a9 17 1 in/out in/out out port m1: i/o port. sei: master output, slave input. address: address bus 9. wuint7 wuint6 wuint5 wuint4 int7 wuint3
tmp92fd54ai 2009-12-26 92fd54ai-7 tentative table 2.2.3 input/output pins (3/4) pin name pin number number of pins in/out function pm2 miso a10 18 1 in/out in/out out port m2: i/o port. sei: master input, slave output. address: address bus 10. pm3 seclk a11 19 1 in/out in/out out port m3: i/o port. sei: clock input/output. address: address bus 11. pm4 sck2 14 1 in/out in/out port m4: i/o port. sbi channel 2: clock input/output at sio mode. pn0 sck0 59 1 in/out in/out port n0: i/o port. sbi channel 0: clock input/output at sio mode. pn1 so0 sda0 60 1 in/out out in/out port n1: i/o port. sbi channel 0: output data input/output at sio mode sbi channel 0: data input/output at i2c mode pn2 si0 scl0 62 1 in/out in in/out port n2: i/o port. sbi channel 0: input data at sio mode sbi channel 0: clock input/output at i2c mode pn3 sck1 a12 64 1 in/out in/out out port n3: i/o port. sbi channel 1: clock input/output at sio mode address: address bus 12. pn4 so1 sda1 a13 65 1 in/out out in/out out port n4: i/o port. sbi channel 1: output data at sio mode sbi channel 1: data input/output at i2c mode address: address bus 13. pn5 si1 scl1 a14 66 1 in/out in in/out out port n5: i/o port. sbi channel 1: input data at sio mode sbi channel 1: clock input/output at i2c mode address: address bus 14 pn6 so2 sda2 a15 67 1 in/out out port n6: i/o port. sbi channel 2: output data at sio mode sbi channel 2: data input output at i2c mode address: address bus 15. nmi 39 1 in non-maskable interrupt: interrupt request pin with programmable falling or both falling and rising edge. int0 37 1 in interrupt request pin 0: interrupt request pin with programmable level or rising-edge. am0,1 80, 78 2 in address mode selection: connect am0 pin to l and am1 pin to h for single chip mode; connect am0 and am1 pins to h for single boot mode. test0,1 76, 71 2 in test mode pins: should be tied to gnd. clk 77 1 out programmable clock output (with pull-up resistor) x1/x2 74, 72 2 in/out high-frequency oscillator connecti ng pins: to drive these pins with an external clock, apply clock signals of 3.3 v. xt1/xt2 70, 69 2 in/out low-frequency oscillator connecting pins: to drive these pins with an external clock, apply clock signals of 3.3 v. reset 79 1 in reset: initializes lsi (with pull-up resistor). vrefh 4 1 in ad reference voltage high vrefl 3 1 in ad reference voltage low advcc 2 1 - power supply pin for ad converter (+5v): connect the advcc pin to 5-v power supply.. advss 1 1 - gnd pin for ad converter: connect the advss pin to gnd (0v). nmi int0
tmp92fd54ai 2009-12-26 92fd54ai-8 tentative table 2.2.4 input/output pins (4/4) pin name pin number number of pins in/out function dvcc5 15, 40, 50, 61, 75 5 - power supply pins (+5v): connect all the dvcc5 pins to 5-v power supply. dvcc3 36, 68, 86 3 - power supply pins (+3.3v): connect all the dvcc3 pins to regout pin. dvss 13, 38, 51, 63, 73, 88 6 - gnd: connect all dvss pins to gnd (0v). regout 49 1 out regulator output 3.3v: connect capacitor to stabilize the regulator output. regen 52 1 in regulator enable pin: should be set to h or open (with pull-up resistor).
tmp92fd54ai 2009-12-26 92fd54ai-9 tentative 3. functional description of flash memory this chapter describes the structure and operations of the internal flash memory. the tmp92fd54ai is a microcontroller incorporatin g a flash memory that is an alternative of the tmp92cd54i?s internal rom. the structural details and functions that are identical with those of the tmp92cd54i are not mentioned in this document. for those details, please refer to the tmp92cd54i datasheet. 3.1 flash memory 3.1.1 features 1) memory capacity the tmp92fd54ai has a 4-mbit (512-kbyte) flash memory, which is divided into a total of ten blocks (64 kbytes 6 blocks, 56 kbytes 2 blocks, 8 kbytes 2 blocks) to allow for independent protection from program and erase for each block. when the cpu attempts to access the internal flash me mory, it uses the 32-bit data bus. 2) flash memory access interleaved access (2-1-1-1 clock access) 3) program/erase time chip programming time: 6 seconds (typ.), including program verify operations [30 s / long word (typ.)] chip erase time: 12 seconds (typ.), in cluding program verify operations 4) programming procedures the device has two on-board programming modes: user boot mode and single boot mode. these modes allow a flash memory to be programmed and erased via a serial communication. ? on-board programming modes 1) us er boot mode (single-chip mode) supports use of a user-written programming algorithm. 2) single boot mode downloads new program code using a toshiba-defined serial interface protocol . user-written programming algorithm is used as the subsequent reprogramming method. 5) program/erase sequence the flash memory contained in the tmp 92fd54ai is compatible with the jedec standards, except a few unique functions. thus, it is easy to change from a discrete flash memory device to the tmp92fd54ai on - chip flash memory. the tmp92fd54ai contains circuitry to perform programming and erase operations automatically. this eliminates the need for the user to code complex program and erase sequences. the tmp92fd54ai allows the user to protect individual blocks of the flash memory against program or erase through software commands; however, does not supported hardware data protection (12-v vpp). for more details, please refer to section 3.5, flash memory program/erase in on-board programming modes. note: these program and erase times are typical values and do not include data transfer overhead. the actual chip program and erase times depend on the programming method used.
tmp92fd54ai 2009-12-26 92fd54ai-10 tentative table 3.1.1 functional differences from the jedec standards jedec standards changes and enhancements ? auto program ? auto chip erase ? auto block erase ? data polling/toggle bit changed feature: block protection is available only under software control. removed feature: erase resume/suspend mode 3.2 block diagram rom c ontr oller / int erleave control mode set-up pin flash memory co ntrol a ddress data flash memory column decoder / sense amp d ata latch address latch erase block decoder control circuit (including automatic sequence control ci rcuit) c ommand register rdy/bsy output internal address bus internal d ata bus internal c ontrol bus flash memory cell 512 k b row decoder mode c ontrol figure 3.2.1 flash memory block diagram
tmp92fd54ai 2009-12-26 92fd54ai-11 tentative 3.3 operating modes 3.3.1 overview the tmp92fd54ai provides two operating modes. table 3.3.1 operating modes operating mode description single-chip mode after a reset, the tmp92fd54ai execut es out of on-chip flash memory. single-chip mode is further divided into normal m ode in which the user applic ation executes and user boot mode which allows for reprogramming of the flash memory while the tmp92fd54ai is installed on a pc board. the means for selecting between these two modes can be set by the user as desired. for example, the logic state on port 00 can be used to determine whether to put the flash memory in normal mode (when port 00 = 1) or user boot mode (when port 00 = 0). the user must include a routine in the app lication program to handle mode switching. normal mode in this mode, the user application program in the flash memory is executed. user boot mode this mode is used to rewrite the fl ash memory while it is installed on a pc board. single boot mode after a reset, the tmp92f d54ai executes out of the on-chip boot rom (which is a mask rom). the boot rom contains an algorithm that allows users to tr ansfer the routine for performing on-board programming of the flash memory via a serial port of the tm p92fd54ai to the on-chip ram. for program/erase operations, the cpu core can issue a command sequence to the flash memory by executing the program/erase routine in the ram while data from an external host is being received. the on-chip flash memory can be reprogrammed in one of the following two modes: user boot mode in single-chip mode and single boot mode. these two modes that allow the user to program and erase the flash memory in user applications are collectively referred to as on-board programming modes. the operating modes for the flash memory, single-chip or single boot mode, is determined by the logic states on the am0, am1, test0 and test1 pins during a reset sequence. the cpu starts operations in each operation mode when the reset state is released after a level input. do not change a mode state while the cpu is running. the operating modes and settings, and th e mode transitions are shown below. table 3.3.2 operating modes input pins operating mode reset am1 am0 test1 test0 (1) single-chip mode (normal and user boot) 1 0 0 0 (2) single boot mode 1 1 0 0 figure 3.3.1 mode transitions reset = l reset = l (2) (1) user-defined condition for mode switching normal mode user boot mode single-chip mode single boot mode single boot mode on-board programming mode reset state parenthesized numbers, (1) and (2), indicate that the relev ant pins are at the logic st ates shown in table 3.3.2.
tmp92fd54ai 2009-12-26 92fd54ai-12 tentative 3.3.2 reset operation to reset the tmp92fd54ai, reset must be asserted for at least 4 s (at f osc = 10 mhz) after the internal oscillator and clock multiplier have stabilized while the supply voltage is kept within the normal operating range. since the clock multiplier is bypassed during reset, the system clock frequency (fc) is set to 5 mhz (when f osc = 10 mhz). for more details, refer to the tmp92cd54i datasheet, section 3.1.2, reset operation. 3.3.3 memory maps in each operating mode the memory map for the tmp92fd54ai varies according to the operation mode. the memory maps, flash memory block architectu re and block addresses for each operation mode are shown below. figure 3.3.2 tmp92fd54ai memory maps single-chip mode single boot mode 000000h 000400h 008400h f80000h ffff00h ffffffh fff000h 000000h 000400h 010000h 090000h fff400h ffff00h ffffffh 008400h on-chip i/o peripherals on-chip ram 32 kb external memory area on-chip flash rom 512 kb ( int vectors 256 b ) on-chip i/o peripherals on-chip ram 32 kb external memory area external memory area reserved on-chip boot rom 3 kb on-chip flash rom 512 kb ( iint vectors 256 b )
tmp92fd54ai 2009-12-26 92fd54ai-13 tentative figure 3.3.3 flash memory block architecture table 3.3.3 block addresses block single-chip mode single boot mode block 0 (64 kb) f80000h - f8ffffh 010000h - 01ffffh block 1 (64 kb) f90000h - f9ffffh 020000h - 02ffffh block 2 (64 kb) fa0000h - faffffh 030000h - 03ffffh block 3 (64 kb) fb0000h - fbffffh 040000h - 04ffffh block 4 (64 kb) fc0000h - fcffffh 050000h - 05ffffh block 5 (64 kb) fd0000h - fdffffh 060000h - 06ffffh block 6 (56 kb) fe0000h - fedfffh 070000h - 07dfffh block 7 (56 kb) fee000h - ffbfffh 07e000h - 08bfffh block 8 ( 8 kb) ffc000h - ffdfffh 08c000h - 08dfffh block 9 ( 8 kb) ffe000h - ffffffh 08e000h - 08ffffh block 0 block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 block 9 64 kb 64 kb 64 kb 64 kb 64 kb 64 kb 56 kb 56 kb 8kb 8kb 512 kb low high addresses
tmp92fd54ai 2009-12-26 92fd54ai-14 tentative 3.4 on-board programming modes (use r boot and single boot modes) on-board programming modes allow for reprogramming of the flash memory while the tmp92fd54ai is soldered on a pc board that enables data communications with external devices. the on-board programming modes include the following: ? user boot mode (supports use of a user-written programming algorithm.) this mode allows flash memory reprogramming by executing a user-written algorithm that is preprogrammed in the flash memory for program and erase operations. this reprogramming operation is initiated by user-defined trigger events. ? single boot mode (supports use of a toshiba-defined boot program.) in this mode, a user-written reprogramming routine is downloaded into the on-chip ram via a toshiba-specified communication pin. the boot program offers operation commands, such as ram transfer and erase. 3.4.1 user boot mode (in single-chip mode) user boot mode allows for flash memory reprogramming by using a user-created reprogramming routine for flash memory. th is mode supports situations where the reprogramming routine that is incorporated in the user application code should be used, and where the data transfer should be performed in mode other than uart mode. this programming algorithm is executed in single-chip mode. to reprogram the flash memory, the mode of operation must be switched from normal mode, in which user application programs usually run, to user boot mode. for example, to let the operation mode to be determined on startup, the user application code must include a mode judgment routine as part of the reset procedure so that the operating mode smoothly changes to user boot mode. the user must define the conditions for mode switching, based on the logic states on i/o ports of the tmp92fd54ai. additionally, the user must incorporate a flash memory programming algorithm into the user applicatio n code that is to be executed after user boot mode is entered. it is impossible to read from the flash memory while it is being erased or programmed; therefore, the programming algorithm must be placed and executed in memory areas that are outside the flash memory, such as on-chip ram. once reprogramming is complete , it is recommended to protect relevant flash blocks from accidental corruption during subseq uent normal mode operations. all interrupts including the nonmaskable interrupt must be globally disabled while the flash memory is being erased or programmed in this mode. when using sio channels, software can check interrupt request flags in interrupt priority level registers, such as intes1, to determine whether reception/transmission has come to an end. the following sections describe the general procedures for two cases where the programming routine is: 1-a) stored within the tmp92fd54ai flash memory, and 1-b) loaded from an external controller. for a detailed descriptions of the erase and program sequence, refer to section 3.5, on-board programming and erasure.
tmp92fd54ai 2009-12-26 92fd54ai-15 tentative 3.4.1.1 (1-a) program/erase procedure 1 this procedure is used when the boot program for flash memory programming and erasure is previously included in the on-chip flash memory. (step 1) building a programming environment determine the conditions (e.g., pin states) required for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the tmp92fd54ai on a pc board, write the following four program routines into an arbitrary flash block in single boot mode. (a) mode judgment routine: code to determine whether or not to switch to user boot mode (b) program/erase routine: code to download new program code from a host controller and reprogram the flash memory (c) copy routine #1: code to copy routines (a) to (d) to either the on-chip ram or external memory device. (d) copy routine #2: code to copy routines (a) to (d) contained in either the on-chip ram or external memory device to the flash memory. note: routine (d) is a code to restore the reprogram ro utines into the flash memory. it is not necessary if routines (a) to (c) are contained in the flash memory after it is reprogrammed. figure 3.4.1 building a programming environment (host controller) new application program code (tmp92fd54ai) flash memory ram [reset procedure] (a) mode judgment routine old application program code (i/o) (b) program/erase routine (c) copy routine #1 (d) copy routine #2
tmp92fd54ai 2009-12-26 92fd54ai-16 tentative (step 2) mode transition to user boot mode (when a mode judgment routine is included as part of the reset procedure boot the tmp92fd54ai in single-chip mode. after a reset, the reset procedure determines whether to put the tmp92fd54ai flash memory in user boot mode by calling a mode judgment routine. if mode switching conditions (e.g., pin states) are met, program execution jumps to user boot program for programming and erasure. (all interrupts including non-maskable interrupt must be glob ally disabled while in user boot mode.) figure 3.4.2 mode transition to user boot mode (step 3) copying the user boot routines to the ram execute copy routine #1 to copy the flash programming routines to either the tmp92fd54ai on-chip ram or an external memory device. (in the following figure, the on-chip ram is used.) note: if routines (a) to (d) are left unerased in the flash memory by using the auto block erase command in step 4, only the program/erase routine (routine (b)) should be copied into the ram. figure 3.4.3 copying the user boot routines to the ram (tmp92fd54ai) flash memory ram [reset procedure] (a) mode judgment routine old application program code (i/o) (b) program/erase routine (c) copy routine #1 (d) copy routine #2 (host controller) new application program code 0 1 reset conditions for entering user boot mode (defined by the user) (tmp92fd54ai) flash memory ram [reset procedure] (a) mode judgment routine old application program code (host controller) new application program code (i/o) (b) program/erase routine (c) copy routine #1 (d) copy routine #2 (a) mode judgment routine (b) program/erase routine (c) copy routine #1 (d) copy routine #2
tmp92fd54ai 2009-12-26 92fd54ai-17 tentative (step 4) erasing the flash memory using the program/erase routine jump program execution to the flash program/erase routine in the on-chip ram to erase the flash memory (with the auto block erase or auto chip erase command) containing the old application program code. figure 3.4.4 erasing the flash memo ry using the program/erase routine (step 5) restoring the user boot routines to the flash memory copy routines (a) to (d) to the flash memory by using copy routine #2 in the on-chip ram. note: step 5 is not required if routines (a) to (d) are kept in the flash memory by using the auto block erase command. figure 3.4.5 restoring the user b oot routines to the flash memory (tmp92fd54 a i) flash memory ram (host controller) new application program code (i/o) (a) mode judgment routine (b) program/erase routine (c) copy routine #1 (d) copy routine #2 erased (tmp92fd54ai) flash memory ram [reset procedure] ( a ) mode jud g ment routine (host controller) new application program code (i/o) ( b ) pro g ram/erase routine ( c ) co py routine #1 ( d ) co py routine #2 ( a ) mode jud g ment routine ( b ) pro g ram/erase routine ( c ) co py routine #1 ( d ) co py routine #2
tmp92fd54ai 2009-12-26 92fd54ai-18 tentative (step 6) writing a new application program code into the flash memory execute the flash program/erase routine in the on-chip ram to download new application program code from the source (host controller) and program it into the erased flash block. figure 3.4.6 writing a new application program code into the flash memory (step 7) executing the new application program code to reset the tmp92fd54ai, drive the reset pin low. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. figure 3.4.7 executing the ne w application program code (tmp92fd54ai) flash memory ram [reset procedure] ( a ) mode jud g ment routine (host controller) new application program code (i/o) ( b ) pro g ram/erase routine ( c ) co py routine #1 ( d ) co py routine #2 ( a ) mode jud g ment routine ( b ) pro g ram/erase routine ( c ) co py routine #1 ( d ) co py routine #2 new application program code (tmp92fd54ai) flash memory ram [reset procedure] new application program code (host controller) (i/o) 0 1 reset conditions for entering normal mode (defined by the user) (a) mode judgment routine (b) program/erase routine (c) copy routine #1 (d) copy routine #2
tmp92fd54ai 2009-12-26 92fd54ai-19 tentative 3.4.1.2 (1-b) program/erase procedure 2 unlike example (1-a), only the essential part of the boot program codes should be incorporated in the flash memory for this method. other programs are supplied from a controller as required upon reprogramming the flash memory. (step 1) building a programming environment determine the conditions (e.g. pin states) re quired for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the tmp92fd54ai on a pc board, write the following two program routines into an arbitrary flash block in single boot mode. (a) mode judgment routine: code to determine whether or not to switch to user boot mode (b) transfer routine: code to download new program/erase code from a host controller prepare the following routines on the host controller: (c) program/erase routine: code to reprogram the flash memory (d) copy routine #1: code to copy routines (a) and (b) to the on-chip ram or external memory device. (e) copy routine #2: code to copy routines (a) and (b) contained in either the on-chip ram or external memory devices to the flash memory. note: routines (d) and (e) are codes to restore t he user boot routines into the flash memory. it is not necessary if routines (a) and (b) are contained in the flash memory after it is reprogrammed. figure 3.4.8 building a programming environment (tmp92fd54ai) (host controller) (i/o) flash memory ram [reset procedure] (a) mode judgment routine old application program code (b) transfer routine new application program code (c) program/erase routine (d) copy routine 1 (e) copy routine 2
tmp92fd54ai 2009-12-26 92fd54ai-20 tentative (step 2) mode transition to user boot mode (when a mode judgment routine is included as part of the reset procedure) boot the tmp92fd54ai in single-chip mode. after a reset, the reset procedure determines whether to put the tmp92fd54ai flash memory in user boot mode by calling a mode judgment routine. if mode switching conditions (e.g., pin states) are met, program execution jumps to user boot program for programming and erasure. (all interrupts including non-maskable interrupt must be glob ally disabled while in user boot mode.) figure 3.4.9 mode transition to user boot mode (step 3) copying the user boot routines from the host controller to the ram execute the transfer routine (routine (b)) to download routines (c) to (e) from the source (host controller) to the on-chip ram or an external memory device. (in the following figure, the on-chip ram is used.) note: if routines (a) and (b) are left unerased in the flash memory by using the auto block erase command in step 5, only the program/eras e routine (routine (c)) should be copied into the on-chip ram. figure 3.4.10 copying the user boot routines in us er boot mode (from the host controller to the ram) (tmp92fd54ai) (host controller) (i/o) 0 1 reset conditions for entering user boot mode (defined by the user) flash memory ram [reset procedure] (a) mode judgment routine old application program code (b) transfer routine new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (tmp92fd54ai) (host controller) (i/o) flash memory ram [reset procedure] (a) mode judgment routine old application program code (b) transfer routine (c) program/erase routine new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (e) copy routine #2 (d) copy routine #1
tmp92fd54ai 2009-12-26 92fd54ai-21 tentative (step 4) copying the user boot routines from the flash memory to the on-chip ram program execution jumps to the routine in the on-chip ram. execute copy routine #1 to copy routines (a) and (b) to the on-chip ram. note: step 4 is not required if routines (a) a nd (b) are kept in the flash memory by using the auto block erase command in step 5. figure 3.4.11 copying the user boot routines (from the flash memory to the on-chip ram) (step 5) erasing the flash memory using the program/erase routine execute the program/erase routine (routine (c)) to erase a flash block or chip containing the old application program code. figure 3.4.12 erasing the flash memory using the program/erase routine (tmp92fd54ai) (host controller) (i/o) flash memory ram [reset procedure] (a) mode judgment routine old application program code (b) transfer routine (c) program/erase routine new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (e) copy routine #2 (d) copy routine #1 (a) mode judgment routine (b) transfer routine new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (tmp92fd54ai) (host controller) (i/o) flash memory ram (c) program/erase routine (e) copy routine #2 (d) copy routine #1 (a) mode judgment routine (b) transfer routine erased
tmp92fd54ai 2009-12-26 92fd54ai-22 tentative (step 6) restoring the user boot routines to the flash memory execute copy routine #2 to copy routines (a) and (b) in the on-chip ram to the flash memory. note: step 6 is not required if routines (a) and (b) are kept in the flash memory by using the auto block erase command in step 5. figure 3.4.13 restoring the user b oot routines to the flash memory (step 7) writing a new application program code into the flash memory execute the flash program/erase routine (c) in the on-chip ram to download new application program code from the source (host controller) and program it into the erased flash block. figure 3.4.14 writing a new applicati on program code into the flash memory (tmp92fd54ai) (host controller) (i/o) flash memory ram [reset procedure] (a) mode judgment routine (b) transfer routine new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (c) program/erase routine (e) copy routine #2 (d) copy routine #1 (a) mode judgment routine (b) transfer routine (i/o) (tmp92fd54ai) flash memory ram [reset procedure] (a) mode judgment routine new application program code (b) transfer routine (host controller) new application program code (c) program/erase routine (d) copy routine #1 (e) copy routine #2 (c) program/erase routine (a) mode judgment routine (b) transfer routine (d) copy routine #1 (e) copy routine #2
tmp92fd54ai 2009-12-26 92fd54ai-23 tentative (step 8) executing the new application program code to reset the tmp92fd54ai, drive the reset pin low. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. figure 3.4.15 executing the new application program code (host controller) (tmp92fd54ai) (i/o) 0 1 reset conditions for entering normal mode (defined by the user) flash memory ram [reset procedure] (a) mode judgment routine new application program code (b) transfer routine
tmp92fd54ai 2009-12-26 92fd54ai-24 tentative 3.4.2 single boot mode in single boot mode, the flash memory can be programmed and erased by using a program contained in the tmp92fd54ai on-chi p boot rom. this boot rom is a masked rom. the flash memory is programmed and er ased by executing a program/erase routine (a user-created reprogramming routine) that is transferred to the ram from an external host controller. in this mode, the on-chip boot rom is mapped to the address area including the interrupt vector table for executing the on-chip boot rom code. the flash memory is mapped to an address space different from the boot rom area (refer to figure 3.3.2). the sio (sio1) of the tmp92fd54ai is connecte d to an external host controller. via this serial link, a programming routine is down loaded from the host controller to the tmp92fd54ai on-chip ram. then, the flash memory is reprogrammed by executing the programming routine. the host sends out both commands and pr ogramming data to reprogram the flash memory. communications between the sio1 and the host must follow the protocol described later. to secure the contents of the flash memory, the validity of the application?s password is checked before a programming routin e is downloaded into the on-chip ram. if password matching fails, the transfer of a programming routine itself is aborted. as in the case of user boot (single-chip) mode, all interrupts including nonmaskable interrupt must be globally disabled in single boot mode while the flash memory is being erased or programmed. when using sio channels, software can check interrupt request flags in interrupt priority level registers, such as intes1, to determine whether reception/transmissi on has come to an end. once reprogramming is complete , it is recommended to protect relevant flash blocks from accidental corruption during subsequent normal mode operations. for a detailed description of the program/erase sequence , refer to section 3.5, flash memory program/erase in on-board programming modes. note: don?t change the pin states of test0, test1, am0 and am1 during a reprogramming operation of the flash memory.
tmp92fd54ai 2009-12-26 92fd54ai-25 tentative 3.4.2.1 using the program/erase routine in the on-chip boot rom (step 1) building a programming environment since a program/erase routine and programming data are transferred via the sio1, the sio1 must be connected to a host controller. prepare a program/erase routine (routine (a)) on the host controller. figure 3.4.16 building a programming environment (step 2) rebooting in single boot mode and the password matching (rebooting from the on-chip rom) reset the tmp92fd54ai with the mode setting pins held at appropriate logic values so that the cpu reboots from the on-chip boot rom. to transfer the program/erase routine (routine (a)) from the source (host controller) to the on-chip ram via the sio, communications are made following the prescribed protocol shown in table 3.4.4. the password transferred from the host controller is first compared to the contents of the special flash memory locations. (if the flash block has already been erased, the password is a sequence of 12 0xff bytes.) for more details on password matching, see section 3.4.2.14, password. figure 3.4.17 rebooting in single boot mode (rebooting from the on-chip rom) (host controller) new application program code (a) program/erase routine (tmp92fd54ai) (i/o) 0 1 reset conditions for entering single boot mode flash memory ram old application program code (or erased state) boot rom sio1 (tmp92fd54ai) flash memory ram old application program code (or erased state) (i/o) boot rom sio1 (host controller) new application program code (a) program/erase routine
tmp92fd54ai 2009-12-26 92fd54ai-26 tentative (step 3) copying the program/erase routine from the host controller to the on-chip ram if the password was correct, the boot rom downloads, via the serial link (sio1), the program/erase routine (routine (a)) from the host controller into the on-chip ram. the program/erase routine must be stored in the address range between 000400h and 006bffh. figure 3.4.18 copying the progr am/erase routine from the host controller to the on-chip ram (step 4) erasing the flash memory by executing the program/erase routine the cpu jumps to the program/erase routine in the on-chip ram to erase the flash block containing the old application program code as required. (the auto block erase or auto chip erase command should be used.) note: since the boot program has the auto chip erase & unprotect commands, the host controller is capable of erasing the flash chip without using the program/erase routine. to perform other operations such as the block erase and block protect operations, corresponding codes should be included in the program/erase routine. figure 3.4.19 erasing the flash memory by executing the program/erase routine (host controller) new application program code (a) program/erase routine (tmp92fd54ai) flash memory ram old application program code (or erased state) (i/o) boot rom sio1 (a) program/erase routine (tmp92fd54ai) flash memory ram (host controller) new application program code (i/o) (a) program/erase routine boot rom sio1 (a) program/erase routine erased
tmp92fd54ai 2009-12-26 92fd54ai-27 tentative (step 5) copying a new application program code next, the program/erase routine (routine (a)) in the on-chip ram downloads a new application program code from the source (host controller) and programs it into the erased flash block. once programming is complete, protection of that flash block is turned on as required. in the example below, a programming data transfer is performed using the same sio communication format as for the program/erase routine. however, once the program/erase routine has been transferred, it is free to change the setting, such as the transfer path and the source of the transfer. create board hardware and a program/erase routine to suit your particular needs. figure 3.4.20 copying a ne w application program code (step 6) executing the new application program when programming of the flash memory is co mplete, power off the board and disconnect the cable leading from the host to the target board. turn on the power again so that the tmp92fd54ai reboots in single-chip mode to execute the new program. figure 3.4.21 executing t he new application program (host controller) (tmp92fd54ai) 0 1 reset conditions for entering single boot mode flash memory ram new application program code boot rom sio1 (tmp92fd54ai) flash memory ram new application program code (host controller) new application program code (i/o) (a) program/erase routine boot rom sio1 (a) program/erase routine
tmp92fd54ai 2009-12-26 92fd54ai-28 tentative 3.4.2.2 connection example in single boot mode in single boot mode, serial transfer is used to reprogram the flash memory while the tmp92fd54ai is installed on the board. in this mode, sio1 of the tmp92fd54ai is connected to a host controller, which is to issue commands to the target board. figure 3.4.22 shows an example of host-to-target connections. figure 3.4.22 example of a connection betwe en a host controller and a target board (when the sio1 is configured for uart mode in single boot mode) target board txd1 (pin 9) rxd1 (pin 8) a m1 (pin 78) dvcc (5 v) vcc pc rs232c rom mode control program controller vcc vcc reg. supply voltage host controller reset am0 mcu mode control interacting with the target board rx vss tx dvss reset (pin 79) boot mode selection logic a m0 (pin 80) ram reg. dvcc (3.3 v) tmp92fd54ai test1 (pin 71) test0 (pin 76) regout (pin 49)
tmp92fd54ai 2009-12-26 92fd54ai-29 tentative 3.4.2.3 mode configuration for on-board programming, boot the tmp92fd54ai in single boot mode as follows: am0, am1 = h; test0, test1 = l; reset = l h set the reset input at logic 0, while setting th e am0, am1, test0 and test1 inputs at the logic values shown above. then release reset (high) so that the tmp92fd54ai reboots in single boot mode. 3.4.2.4 memory map figure 3.4.23 shows a comparison of the me mory maps in single-chip and single boot modes. in single boot mode , the on - chip flash memory is mapped to the addresses 010000h through 08ffffh; while the on - chip boot rom (masked rom) is mapped to the addresses fff400h through ffffffh. figure 3.4.23 memory maps (for single-chip and single boot modes) single-chip mode single boot mode 000000h 000400h 008400h f80000h ffff00h ffffffh fff000h 000000h 000400h 010000h 090000h fff400h ffff00h ffffffh 008400h on-chip i/o peripherals on-chip ram 32 kb external memory area on-chip flash rom 512 kb ( int vectors 256 b ) on-chip i/o peripherals on-chip ram 32 kb external memory area external memory area reserved on-chip boot rom 3 kb on-chip flash rom 512 kb ( int vectors 256 b )
tmp92fd54ai 2009-12-26 92fd54ai-30 tentative 3.4.2.5 interface specification the sio communication format in single boot mode is shown below. the serial transfer supports the uart (asynchronous) mode. to perform on-board programming, the host controller must also be configured to use the following communication format. ? uart mode communication channel: sio channel 1 serial transfer mode: uart (asynchronous) mode, full-duplex data length: 8 bits parity bits: none stop bits: 1 bit baud rate: refer to table 3.4.1 table 3.4.1 selective baud rates baud rate (bps) 38400 19200 9600 4800 2400 table 3.4.2 pin connections required in single boot mode dvcc3/5 (3.3/5.0 v) power supply pins dvss mode-setting pins am1, am0, test1, test0 reset pin reset txd1 communications pins rxd1 3.4.2.6 data transfer formats operation commands and data transfer format s for each operation mode are shown in table 3.4.3 through table 3.4.7. at the same time, read the descriptions on the boot program commands described later. table 3.4.3 operation commands code command 10h ram transfer 20h show flash memory sum 30h show product information 40h auto chip erase & unprotect
tmp92fd54ai 2009-12-26 92fd54ai-31 tentative table 3.4.4 transfer format for the ram transfer command byte data transferred from the controller to the tmp92fd54ai baud rate data transferred from the tmp92fd54ai to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) 3rd byte command code (10h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 5th byte thru 16th byte password sequence (12 bytes) (08fef4h thru 08feffh) ? 17th byte checksum value for bytes 5 - 16 ? 18th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge 11h communication error 18h 19th byte ram storage start address (bits 31-24) (note 3) ? 20th byte ram storage start address (bits 23-16) (note 3) ? 21st byte ram storage start address (bits 15-8) (note 3) ? 22nd byte ram storage start address (bits 7-0) (note 3) ? 23rd byte ram storage byte count (bits 15-8) (note 3) ? 24th byte ram storage byte count (bits 7-0) (note 3) ? 25th byte checksum value for bytes 19-24 (note 3) ? 26th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge 11h communication error 18h 27th byte thru mth byte ram storage data ? (m + 1)th byte checksum value for bytes 27-m ? (m + 2)th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge 11h communication error 18h ram (m + 3)th byte ? jump to ram storage start address note 1: for baud rate options, see table 3.4.1. note 2: in case of any negative acknowledge the boot program returns to a state in which it waits for a command code (the 3rd b yte). note 3: the 19th to 25th bytes must be within the ram address range between 000400h and 006bffh.
tmp92fd54ai 2009-12-26 92fd54ai-32 tentative table 3.4.5 transfer format for the show flash memory sum command byte data transferred from the controller to the tmp92fd54ai baud rate data transferred from the tmp92fd54ai to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) 3rd byte command code (20h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 20h negative acknowledge x1h communication error x8h 5th byte ? sum (upper byte) 6th byte ? sum (lower byte) 7th byte ? checksum value for bytes 5 and 6 8th byte (wait for the next command code.) ? note 1: for baud rate options, see table 3.4.1. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (the 3rd byte).
tmp92fd54ai 2009-12-26 92fd54ai-33 tentative table 3.4.6 transfer format for the show product information command (1 of 2) byte data transferred from the controller to the tmp92fd54ai baud rate data transferred from the tmp92fd54ai to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h ? 2nd byte ? ack for the serial operation mode byte for uart normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) 3rd byte command code (30h) desired baud rate (note 1) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 30h negative acknowledge x1h communication error x8h 5th byte ? flash memory data (at address 08fef0h) 6th byte ? flash memory data (at address 08fef1h) 7th byte ? flash memory data (at address 08fef2h) 8th byte ? flash memory data (at address 08fef3h) 9th byte thru 20th byte ? product name (12-byte ascii code) tmp92fd54ai_ from the 9th byte (where _ denotes a space) 21st byte thru 24th byte ? password comparison start address (4 bytes) f4h, feh, 08h and 00h from the 21st byte 25th byte thru 28th byte ? ram start address (4 bytes) 00h, 04h, 00h and 00h from the 25th byte 29th byte thru 32nd byte ? dummy data (4 bytes) feh, 6bh, 00h and 00h from the 29th byte 33rd byte thru 36th byte ? ram end address (4 bytes) ffh, 83h, 00h and 00h from the 33rd byte 37th byte thru 40th byte ? dummy data (4 bytes) 00h, 00h, 00h and 00h from the 37th byte 41st byte thru 44th byte ? dummy data (4 bytes) 00h, 00h, 00h and 00h from the 41st byte 45th byte thru 46th byte ? protect status (2 bytes) from the 45th byte protected 00h, 03h not protected 00h, 01h 47th byte thru 50th byte ? flash memory start address (4 bytes) 00h, 00h, 01h and 00h from the 47th byte 51st byte thru 54th byte ? flash memory end address (4 bytes) ffh, ffh, 08h and 00h from the 51st byte 55th byte thru 56th byte ? flash memory block count (2 bytes) 0ah and 00h from the 55th byte 57th byte thru 60th byte ? start address of a group of the same-size flash blocks (4 bytes) 00h, 00h, 01h and 00h from the 57th byte
tmp92fd54ai 2009-12-26 92fd54ai-34 tentative table 3.4.7 transfer format for the show product information command (2 of 2) byte data transferred from the controller to the tmp92fd54ai baud rate data transferred from the tmp92fd54ai to the controller boot rom 61st byte thru 64th byte ? size (in words) of the same-size flash blocks (4 bytes) 00h, 80h, 00h and 00h from the 61st byte 65th byte ? number of flash blocks of the same-size flash blocks (1 byte) 06h 66th byte thru 69th byte ? start address of a group of the same-size flash blocks (4 bytes) 00h, 00h, 07h and 00h from the 66th byte 70th byte thru 73rd byte ? size (in words) of the same-size flash blocks (4 bytes) 00h, 70h, 00h and 00h from the 70th byte 74th byte ? number of flash blocks of the same-size flash blocks (1 byte) 02h 75th byte thru 78th byte ? start address of a group of the same-size flash blocks (4 bytes) 00h, c0h, 08h and 00h from the 75th byte 79th byte thru 82nd byte ? size (in words) of the same-size flash blocks (4 bytes) 00h, 10h, 00h and 00h from the 79th byte 83rd byte ? number of flash blocks of the same-size flash blocks (1 byte) 01h 84th byte ? checksum value for bytes 5 to 83 85th byte (wait for the next command code) desired baud rate (note 1) ? note 1: for baud rate options, see table 3.4.1. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (the 3rd byte).
tmp92fd54ai 2009-12-26 92fd54ai-35 tentative table 3.4.8 transfer format for the auto chip erase & unprotect command byte data transferred from the controller to the tmp92fd54ai baud rate data transferred from the tmp92fd54ai to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) 3rd byte command code (40h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 40h negative acknowledge x1h communication error x8h 5th byte ? ack for the erase commands normal acknowledge 4fh negative acknowledge 4ch 6th byte ? ack normal acknowledge b1h negative acknowledge b4h 7th byte (wait for the next command code) ? note 1: for baud rate options, see table 3.4.1. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (the 3rd byte). 3.4.2.7 boot program when single boot mode is selected, the boot program is automatically executed on startup. the boot program offers the following commands: 1. ram transfer command the ram transfer command stores program code (user program code) transferred from a host controller to the on-chip ram. the cpu then jumps to the ram storage start address and executes the program once the transfer is successfully completed. the user program of up to 26 kbytes can be transferred. (the size is limited by the boot program for the protection of stack area and other areas. once the ram transfer command is completed, the whole on-chip ram is accessible.) the ram transfer command can be used to download a flash program/erase routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. the program/erase routine must utilize the flash memory command sequences described in section 3.5, flash memory program/erase in on-board programming modes. before initiating a transfer, the ra m transfer command checks a password sequence coming from the controller against that stored in the flash memory. if they do not match, the ram transfer command aborts and the boot program waits for the next command code.
tmp92fd54ai 2009-12-26 92fd54ai-36 tentative 2. show flash memory sum command the show flash memory sum command adds the contents of the 512 kbytes of the flash memory together and returns the sum result. the boot program does not provide a command to read out the contents of the whole area in the flash memory. instead, the show flash memory sum command can be us ed for software revision management. 3. show product information command the show product information command provides information like a product name and on-chip memory configuration. this co mmand also reads out the contents of the given flash memory locations at addresses 08fef0h to 08fef3h. in addition to the show flash memory sum command, these locati ons can be used for software revision management. 4. auto chip erase & unprotect command the auto chip erase & unprotect command er ases all blocks in the flash memory. if some blocks are protected, executing this command resets the all block-protection setting and erasing all blocks in the flash memory. since this command also serves to restore the boot program in case that a user forgets the password, password matching is not performed.
tmp92fd54ai 2009-12-26 92fd54ai-37 tentative 3.4.2.8 ram transfer command (see table 3.4.4) 1. from host controller to target board the 1st byte determines the operation mode and baud rate. during the first-byte interval, sc1mod0 is cleared to disable the sio1 reception. the boot program monitors the logic state of the rxd1 pin and calculates the baud rate. ? communication in uart mode send, from the controller to the target board, 86h in uart data format at the desired baud rate. if the serial operation mode is determined as uart, then the boot program checks if the sio1 can be programmed to the baud rate at which the 1st byte was transferred. if the first byte is not identified as 86h, or if that baud rate is not possible, the boot program aborts, disabling any subsequent communications. 2. from target board to host controller the 2nd byte is an acknowledge (ack) response to the 1st byte, which specifies the serial operation mode. if the first byte is determined to specify uart mode, and also if the sio1 is programmable at the desired baud rate, the boot program sends back 86h to the controller. ? baud rate determination according to the baud rate value calculated based on the first byte, the tmp92fd54ai checks if the sio1 is programmable at the desired baud rate. if it is determined as possible, the on-chip boot program sets the baud rate value in the br1cr and br1add registers and sends back 86h in uart data format after enabling the sio1 recept ion by setting sc1mod0. if the sio1 is not programmable at that baud rate, the boot program simply aborts without any error indication. the controller allows for a time-out period of five seconds after the transmission of a first byte is complete d. if 86h is not received within the allotted time-out period, the controller should give up the communication. 3. from host controller to target board the 3rd byte is an operation command data. the code for the ram transfer command is 10h, which is tran smitted from the controller. 4. from target board to host controller the 4th byte is an ack response to the 3rd byte. its upper four bits hold the same values as the upper four bits of the previously issued command. before sending back the ack, the boot program checks for a receive error. if there was a receive error, the boot program transmits x8h (bit 3 = 1) and returns to the state in which it waits for a command (the 3rd byte) again. if the 3rd byte is equal to any of the command codes listed in table 3.4.3, the boot program echoes it back to the controller as a normal ack. when the ram transfer command was received, the boot program echoes back a value of 10h and then branches to the ram transfer routine. once this branch is taken, a password check is done. password checking is detailed in section 3.4.2.14, password. if the 3rd byte is not a valid command, the boot program sends back x1h (bit 1 =
tmp92fd54ai 2009-12-26 92fd54ai-38 tentative 1) as an invalid command error response and returns to the state in which it waits for a command (the 3rd byte) again. 5. from host controller to target board the 5th to 16th bytes are a 12-byte password. the 5th byte is compared to the contents of address 08fef4h in the flash memory; the 6th byte is compared to the contents of address 08fef5h in the fl ash memory; likewise, the 16th byte is compared to the contents of address 08feffh in the flash memory. 6. from host controller to target board the 17th byte is a checksum value for the password sequence (5th to 16th bytes). to calculate the checksum value for the 12-byte password, add all these bytes (unsigned addition), drop the carries and take the two?s complement of the lower 8 bits of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in detail in section 3.4.2.16, checksum calculation. 7. from target board to host controller the 18th byte is an ack response to the 5th to 17th bytes (ack for the checksum byte). its upper four bits are the same as those of the previously issued command, 0001b. first, the ram transfer routine checks for a receive error in the 5th to 17th bytes. if there was a receive error, the boot program sends back 18h (bit 3 = 1) as a communication error response and returns to the state in which it waits for the next command (the 3rd byte) again. next, the ram transfer routine performs the checksum operation to ensure data integrity. adding the series of the 5th to 17th bytes (8-bit unsigned addition with the carry dropped) must result in 00h. if it is not 00h, the ram transfer routine sends back 11h (bit 0 = 1) as a ch ecksum error response to the controller and returns to the state in which it waits for a command (the 3rd byte) again. finally, the ram transfer routine examines the result of the password check. the following case is treated as a password error. in this case, the ram transfer routine sends back 11h (bit 0 = 1) to the controller as a password error response and returns to the state in which it waits for a command (the 3rd byte) again. z not the entire password bytes transmitte d from the controller matched those contained in the flash memory. when all the above checks have been successful , the ram transfer routine returns a normal ack ( 10h ) to the controller. 8. from host controller to target board the 19th to 22nd bytes indicate the start address of the ram region where subsequent data should be stored. the 19th byte corresponds to bits 31-24 of the address, the 20th byte corresponds to bits 23-16 of the address, the 21st byte corresponds to bit 15-8 and the 22nd byte corresponds to bits 7-0 of the address. the start address, transmitted to the target board, must be within the ram address range 000400h-006bffh. 9. from host controller to target board the 23rd and 24th bytes indicate the number of bytes that will be transferred in
tmp92fd54ai 2009-12-26 92fd54ai-39 tentative blocks from the controller to be stored in the ram. the 23rd byte corresponds to bits 15-8; while the 24th byte corresponds to bits 7-0. the byte count, transmitted to the target board, must be within the ram address range 000400h-006bffh. 10. from host controller to target board the 25th byte is a checksum value for the 19th to 24th bytes. to calculate the checksum value, add all these bytes together (unsigned addition), drop the carries and take the two?s complement of the lower 8 bits of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in detail in section 3.4.2.16, checksum calculation. 11. from target board to host controller the 26th byte is an ack response to the 19th to 25th bytes (ack for the checksum byte). its upper four bits are the same as those of the previously issued command, 0001b. first, the ram transfer routine checks fo r a receive error in the 19th to 25th bytes. if there was a receive error, the ram transfer routine sends back 18h (bit 3 = 1) as a communication error response and returns to the state in which it waits for a command (the 3rd byte) again. next, the ram transfer routine performs the checksum operation to ensure data integrity. the checksum value for the 19th to 25th bytes (8-bit unsigned addition with the carry dropped) must re sult in 00h. if it is not 00h, the ram transfer routine sends back 11h (bit 0 = 1) to the controller as a checksum error response, and returns to the state in which it waits for a command (the 3rd byte) again. when the above checks have been successful, the ram transfer routine returns a normal ack (10h) to the controller. 12. from host controller to target board the 27th to mth bytes from the controller are stored in the tmp92fd54ai on-chip ram. storage begins at the address specified by the 19th to 22nd bytes and continues for the number of bytes specified by the 23rd and 24th bytes. 13. from host controller to target board the (m+1)th byte is a checksum value. to calculate the checksum value, add the 27th to mth bytes together (8-bit unsigned addition with the carry dropped) and take the two?s complement of the lower 8 bits of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in detail in section 3.4.2.16, checksum calculation. 14. from target board to host controller the (m+2)th byte is an ack response to the 27th to (m+1)th bytes (ack for the checksum byte). its upper four bits are th e same as those of the previously issued command, 0001b. first, the ram transfer routine checks for a receive error in the 27th to (m+1)th bytes. if there is a receive error, the ram transfer routine sends back 18h (bit 3 = 1) as a communication error response, and returns to the state in which it waits for a command (the 3rd byte) again.
tmp92fd54ai 2009-12-26 92fd54ai-40 tentative next, the ram transfer routine performs the checksum operation to ensure data integrity. the checksum value for the 27th to (m+1)th bytes (8-bit unsigned addition with the carry dropped) must result in 00h. if it is not 00h, the ram transfer routine sends back 11h (bit 0 = 1) to the controller as a checksum error response, and returns to the state in whic h it waits for a command (the 3rd byte) again. when the above checks have been successful, the ram transfer routine returns a normal ack (10h) to the controller. 15. from target board to host controller if the (m+2)th byte is a normal ack, a branch is made to the address specified by the 19th to 22nd bytes after sending a normal ack (10h). 3.4.2.9 show flash memory sum command (see table 3.4.5) 1. the processing of the 1st and 2nd bytes are the same as for the ram transfer command. 2. from host controller to target board the 3rd byte is a command code. the code for the show flash memory sum command is 20h. 3. from target board to host controller the 4th byte is an ack response to the 3rd byte. its upper four bits hold the same values as the upper four bits of the previously issued command. before sending back the ack, the boot program checks for a receive error. if there was a receive error, the boot program transmits x8h (bit 3 = 1) as a communication error response, and returns to the state in which it waits for a command (the 3rd byte) again. if the 3rd byte is equal to any of the command codes listed in table 3.4.3, the boot program echoes it back as the normal ack to the controller. in this case, the boot program echoes back a value of 20h and then branches to the show flash memory sum routine. if the 3rd byte is not a valid command , the boot program sends back x1h (bit 0 = 1) to the controller as an invalid command error response, and returns to the state in which it waits for a command (the 3rd byte) again. 4. from target board to host controller the show flash memory sum routine adds all the bytes of the flash memory together. the 5th and 6th bytes indicate the upper and lower bytes of this total sum respectively. for details on sum calcul ation, see section 3. 4.2.15, calculation of the show flash memory sum command. 5. from target board to host controller the 7th byte is a checksum value for th e 5th and 6th bytes. to calculate the checksum value, add the 5th and 6th bytes (8-bit unsigned addition with the carry dropped), and take the two?s complement of the lower 8 bits of the total sum. transmit this checksum value from the controller to the target board. the target board waits for the next command code after transmitting the 7th byte.
tmp92fd54ai 2009-12-26 92fd54ai-41 tentative 3.4.2.10 show product information co mmand (see table 3.4.6 and table 3.4.7) 1. the processing of the 1st and 2nd bytes are the same as for the ram transfer command. 2. from host controller to target board the 3rd byte is a command code. the co de for the show product information command is 30h. 3. from target board to host controller the 4th byte is an ack response to the 3rd byte. its upper four bits hold the same values as the upper four bits of the previously issued command. before sending back the ack, the boot program checks for a receive error. if there was a receive error, the boot program transmits x8h (bit 3 = 1) as a communication error response, and returns to the state in which it waits for a command (the 3rd byte) again. if the 3rd byte is equal to any of the command codes listed in table 3.4.3, the boot program echoes it back to the controller as a normal ack. in this case, the boot program echoes back a value of 30h and then branches to the show product information routine. if the 3rd byte is not a valid command , the boot program sends back x1h (bit 0 = 1) to the controller as invalid command e rror response, and returns to the state in which it waits for a command (the 3rd byte) again. 4. from target board to host controller the 5th to 8th bytes are the data read from the addresses 08fef0h to 08fef3h in the flash memory. software version management is possible by storing a software id in these locations. 5. from target board to host controller the 9th to 20th bytes indicate the product name, which is tmp92fd54ai_ in ascii code (where _ denotes a space). 6. from target board to host controller the 21st to 24th bytes indicate the password comparison start address, i.e., f4h, feh, 08h, 00h. 7. from target board to host controller the 25th to 28th bytes indicate the start address of the on-chip ram, i.e., 00h, 04h, 00h, 00h. 8. from target board to host controller the 29th to 32nd bytes are the end address of the on-chip ram (in the user area), i.e., ffh, 6bh, 00h, 00h. 9. from target board to host controller the 33rd to 36th bytes indicate the end address of the on-chip ram, i.e., ffh, 83h, 00h, 00h.
tmp92fd54ai 2009-12-26 92fd54ai-42 tentative 10. from target board to host controller the 37th to 44th bytes are dummy data. 11. from target board to host controller the 45th and 46th bytes indicate protect status of blocks in the flash memory. if any of blocks 0 to 9 is protected, th e 45th and 46th bytes contain 00h and 01h respectively. if all blocks are unprotected, they contain 00h and 03h respectively. 12. from target board to host controller the 47th to 50th bytes indicate the start address of the on-chip flash memory, i.e., 00h, 00h, 01h, 00h. 13. from target board to host controller the 51st to 54th bytes indicate the end address of the on-chip flash memory, i.e., ffh, ffh, 08h, 00h. 14. from target board to host controller the 55th and 56th bytes indicate the numbe r of flash memory blocks available, i.e., 0ah, 00h. 15. from target board to host controller the 57th to 83rd bytes contain information about the flash blocks. flash blocks of the same size are treated as a group. information about the flash blocks indicate the start address of a group, the si ze of the blocks in that group (in words) and the number of the blocks in that group. the 57th to 65th bytes are the information about the 64-kbyte blocks (block 0 to block 5); the 66th to 74th bytes are the information about the 56-kbyte blocks (blocks 6 and 7); the 75th to 83rd bytes are the information about the 8-kbyte blocks (blocks 8 and 9). for the values of the transmitted bytes, refer to table 3.4.6 and table 3.4.7. 16. from target board to host controller the 84th byte is a checksum value for the 5th to 83rd bytes. the checksum value is calculated by adding all these bytes together (8-bit unsigned addition with the carry dropped) and taking the two?s complement of the lower 8 bits of the total sum. the checksum value is transmitted from the controller to the target board. the target board waits for the next command code after transmitting the 84th byte.
tmp92fd54ai 2009-12-26 92fd54ai-43 tentative 3.4.2.11 auto chip erase & unprotec t command (refer to table 3.4.8) 1. the processing of the 1st and 2nd bytes are the same as for the ram transfer command. 2. from host controller to target board the 3rd byte indicates a command code. the code for the auto chip erase & unprotect command is 40h. 3. from target board to host controller the 4th byte is an ack response to the 3rd byte. its upper four bits hold the same values as the upper four bits of the previously issued command. before sending back the ack, the boot program checks for a receive error. if there was a receive error, the boot program transmits x8h (bit 3 = 1) as a communication error response, and returns to the state in which it waits for a command (the 3rd byte) again. if the 3rd byte is equal to any of the command codes listed in table 3.4.3, the boot program echoes it back to the controller as a normal ack. in this case, the boot program echoes back a value of 40h and then branches to the auto chip erase & unprotect routine. if the 3rd byte is not a valid command , the boot program sends back x1h (bit 0 = 1) to the controller as an invalid command error response, and returns to the state in which it waits for a command (the 3rd byte) again. 4. from target board to host controller the 5th byte indicates whether the auto chip erase processing is properly completed. if it is completed, the end code (4fh) is sent back; while the error code (4ch) is sent back for processing error. 5. from target board to host controller the 6th byte is an ack response. if a command is completed, the end code (b1h) is sent back as a normal ack. if an error occurs, the error code (b4h) is sent back as an erase error response. the target board waits for the next command code after transmitting the 6th byte.
tmp92fd54ai 2009-12-26 92fd54ai-44 tentative 3.4.2.12 acknowledge (ack) responses the boot program represents processing states with specific codes. table 3.4.9 to table 3.4.12 show the values of possible ack responses to the received data. the upper four bits of the ack are equal to those of the command being executed. bit 3 of the code indicates a receive error. bit 0 indicates an invalid co mmand error, a checksum error or a password error. bit 1 and bit 2 are always 0. table 3.4.9 ack response to the serial operation mode byte return value meaning 86h the sio can be configured to operate in uart mode. (note 1) note 1: if the sio is not programmable at the baud rate , the program simply aborts with no error indication. table 3.4.10 ack response to the command byte return value meaning x8h (note 2) a receive error occurred while getting a command code. x1h (note 2) an undefined command code was received. 10h the ram transfer command was received. 20h the show flash memory sum command was received. 30h the show product information command was received. 40h the auto chip erase & unprotect command was received. note 2: the upper four bits of the ack are the same as those of the previous command code. table 3.4.11 ack response to the checksum byte return value meaning 18h a receive error occurred. 11h a checksum error or password error occurred. 10h the checksum was correct. table 3.4.12 ack response to the auto chip erase & unprotect byte return value meaning 4fh, b1h an erase operation was properly completed. 4ch, b4h an erase error occurred.
tmp92fd54ai 2009-12-26 92fd54ai-45 tentative 3.4.2.13 automatic baud rate programming for uart mode the controller must first send a value of 86h at a desired baud rate to the target board in uart data format. the waveform of the fi rst byte, 86h, is shown in figure 3.4.24. figure 3.4.24 serial operation mode byte, 86h after reset is released, the boot program does not receive the first serial byte (86h) from the controller as a serial receive data. th e boot program monitors the logic states of the rxd1 pin and captures timer counts each time a logic transition of the pin occurs. the boot program calculates the intervals of tab, tac and tad. then, the serial operation mode is determined as uart mode. at the same time, the boot program determines whether the auto programming of baud rate is possible or not. if the controller fails to receive an echo-back (86h), or if the boot program determines that the sio is not programmable at the baud rate, the controller should give up further communication. uart (86h) point a point b point c point d bit 7 bit 0 bit 1 bit 2 bit 4 bit 5 bit 6 start stop bit 3 tad tac
tmp92fd54ai 2009-12-26 92fd54ai-46 tentative 3.4.2.14 password the ram transfer command (10h) causes the boot program to perform a password check. following an echo-back of the command code, the boot program checks the contents of the 12-byte password area (8fef4h to 8feffh) within the flash memory. the password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. table 3.4.13 shows how they are compared byte-by-byte. all of the 12 bytes must match to pass the password check. otherwise, a password error occurs, which causes the boot program to return an error acknowledge at the 18th byte in response to the checksum byte (the 17th byte). table 3.4.13 relationship between received bytes and flash memory locations received byte compared flash memory data 5th byte address 08fef4 6th byte address 08fef5 7th byte address 08fef6 8th byte address 08fef7 9th byte address 08fef8 10th byte address 08fef9 11th byte address 08fefa 12th byte address 08fefb 13th byte address 08fefc 14th byte address 08fefd 15th byte address 08fefe 16th byte address 08feff
tmp92fd54ai 2009-12-26 92fd54ai-47 tentative 3.4.2.15 calculation of the show flash memory sum command the show flash memory sum command adds all 512 kbytes of the flash memory together by performing an 8-bit unsigned addi tion, and provides the total sum as a word quantity. the sum is sent to the controller with the upper eight bits first, followed by the lower eight bits. the sum returned in respon se to the show flash memory sum command is calculated in this way. example: 3.4.2.16 checksum calculation the checksum byte for a series of bytes of data is calculated by adding the bytes together (8-bit unsigned addition with the carry dropped), and taking the two?s complement of the lower 8 bits. the show flash memory sum command and the show product information command perform the checksum calculation. the controller must perform the same checksum operation when transmitting checksum bytes. example: assume the show flash memory sum command provides the upper and lower bytes of the sum as e5h and f6h. to calculate the checksum for a series of e5h and f6h: add the bytes together (using an 8-bit unsigned addition). e5h + f6h = 1dbh take the two?s complement of the sum of the lower 8 bits, and that is the checksum byte. hence, 25h is sent to the controller. 0 ? dbh = 25h a1h b2h c3h d4h for the interest of simplicity, assume the depth of the flash memory is four locations as shown in the figure on the left. then the sum of the four bytes is calculated as: a1h + b2h + c3h + d4h = 02eah hence, 02h is first sent to the controller, followed by eah.
tmp92fd54ai 2009-12-26 92fd54ai-48 tentative 3.4.2.17 general boot program flowchart figure 3.4.25 shows an overall flowchart of the boot program. figure 3.4.25 overall boot program flow initialize single boot program starts get sio operation mode data prepare to get a command ack data ack data & f0h uart receive routine get a command no receive error? ram transfer? ack data received data (10h) transmit routine send 10h normal response yes (10h) ram transfer processing processed normally? jump to ram ye s ack data ack data x8h transmit routine send x8h receive erro r show flash memory sum? command error yes (20h) ack data received data (20h) ack data ack data 01h transmit routine send 20h normal response transmit routine send x1h command error flash memory sum processing yes show product information? ye s ( 30 h) ack data received data (30h) transmit routine send 30h normal response product information processing baud rate pro g rammin g ? program uart mode and baud rate ack data received data ( 86h ) (send 86h) normal res p onse stop operation not programmable programmable auto chip erase & unprotect? yes (40h) ack data received data (40h) auto chip erase & unprotect processing transmit routine send 40h normal res p onse no no no no
tmp92fd54ai 2009-12-26 92fd54ai-49 tentative 3.5 flash memory program/erase in on-board programming modes the tmp92fd54ai flash memory is command set compatible with the jedec eeprom standard. the flash memory can be programmed and erased by the cpu executing software commands. because the flash memory cannot be read while it is being programmed or erased, the program/erase routine must be stored in the on-chip ram or an external memory device. note: it is the user?s re sponsibility to prepare a program/erase routine. 3.5.1 key features the tmp92fd54ai flash memory commands ar e in principle compatible with the standard jedec commands with a few exce ptions. the system can issue a command sequence to the flash memory by using cpu instructions such as ld. according to the written command sequence, the flash memory initiates the embedded program or erase algorithm automatically. table 3.5.1 flash memory features feature description auto program programs and verifies the specified addre sses in longword (32-bit) quantities automatically. auto chip erase erases and verifies the entire memory array automatically. auto block erase erases and verifies all memory locations in the selected block automatically. hardware sequence flag provides severa l status bits such as the data po lling bit, which can be used to determine whether a program or erase operation is complete or in progress. block protect disables both program and erase operations in any block. auto chip erase & unprotect erases the entire memo ry array and unprotects all blocks automatically. due to the on-chip cpu interface, the tmp92fd54ai uses addresses different from those of the jedec standard flash command sequences. unless otherwise noted, programming is done in 32-bit quantities; thus the 32-bit load instruction should be used. the byte (8-bit) load instruction can be used to issue commands to the flash memory.
tmp92fd54ai 2009-12-26 92fd54ai-50 tentative 3.5.2 block architecture single-chip single boot f80000h 010000h 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 56 kbytes 56 kbytes 8 kbytes ffffffh 8 kbytes 08ffffh figure 3.5.1 flash memory block architecture 3.5.3 internal cpu-to-flash interface figure 3.5.2 illustrates the internal interf ace between the cpu and the flash memory of the tmp92fd54ai. the diagram does not show the actual logic network; instead it is only a conceptual depiction of the cpu-to-flash interface. figure 3.5.2 internal cpu-to-flash interface decoder operation mode flash memory dq31 ? dq0 d31 ? d0 a31 ? a17 a16 ? a2 ad14 ? ad0 cpu ce we oe wr rd single-chip mode: f80000h to ffffffh single boot mode: 010000h to 08ffffh r/bsy reset cpu reset (512 kb) register
tmp92fd54ai 2009-12-26 92fd54ai-51 tentative 3.5.4 read mode and automatic operation mode the flash memory of the tmp92fd54ai has the following two operation modes: ? read mode: array data is read. (the flash memory cannot be reprogrammed in this mode.) ? automatic operation mode: the flash array is automatically programmed or erased. (array data cannot be read in this mode.) the flash memory enters automatic operation mode when a valid command is executed in read mode. 1) read for data read operations, the flash memory enters read mode upon the following conditions: a) the automatic operation is successfully completed. b) hardware reset (include the cpu internal reset) c) software reset (read/reset command) 2) writing commands the tmp92fd54ai flash memory is command set compatible with the jedec eeprom standard. write operations to the internal command register is performed by executing command sequences to the flash memory. the flash memory executes command sequences by latching the written addresses and data into the command register. (see table 3.5.3 and table 3.5.4.) commands are written via dq0-dq7 except the fourth (read) cycle in the read/reset command sequence, the fourth (write) cycle in the auto program command sequence and the fourth (write) cycle in the verify block protect command sequence. thus, commands can be provided byte by byte. the command sequence being written can be canceled by issuing the read/reset command between sequence cycl es. the read/reset command clears the command register and resets the flash memory to read mode. 3) reset resetting the flash memory can put it back into read mode. the flash memory should be reset after executing the verify block protect command, or if an automatic operation of the flash memory terminated abnormally. ? read/reset command (software reset) the read/reset command must be issued to initialize the internal circuitry of the flash memory and put the flash memory back in read mode. since the flash memory disables command sequence receptions while an automatic operation is in progress, the flash memory cannot be reset with th e read/reset command during that period. ? hardware reset ( reset pin input) asserting the reset pin initializes the internal circuitry of the flash memory and puts it back to read mode by hardware. as shown in figure 3.5.2, the flash memory has a reset pin, which is connected to the reset signal of the cpu. when the system drives the reset pin to v il or when certain events such as a watchdog timer time-out causes a cpu reset, a hardware reset is performed on the flash memory.
tmp92fd54ai 2009-12-26 92fd54ai-52 tentative a hardware reset operation immediately terminates any operation in progress and the flash memory is reset to read mode. if a hardware reset is performed in the middle of an automatic operation, the flash memory data might be corrupted due to an abort of any ongoing operation, such as program and erase operations. thus, after performing a hardware reset, it should be checked whether there is any change in the entire memory array and their protect status. 4) auto program command the auto program operation cannot overwrite programmed memory locations. a bit must be programmed to change its state from a 1 to a 0. a bit cannot be programmed from a 0 back to a 1. only an auto erase operation can change a 0 back to a 1. in on-board programming mo des, the auto program command programs the desired addresses in longword (3 2-bit) quantities. thus, the program address must be a multiple of four. the auto program command requires four bus cycles; the program address and data are written in the fourth cycle, upon completion of which the program operation will commence. the auto program command executes a sequence of events to program the desired bits of the addressed memory location and verify that the desired bits are sufficiently programmed. the block protection feature disables programming operations in any block. if an attempt is made to program a protected block, the auto program command does nothing; the flash memory returns to read mode in approximately 3 s after the completion of the fourth bus cycle of the command sequence. any commands written during the programming operation are ignored. the system can determine the status of the programming operations by using write status flags and the flsr bit. when the embedded auto program algorithm is complete, the flash memory returns to read mode. if any failure occurs during the programming operation, the flash memory remains locked in automatic operation mode. the system can determine this status by using write status flags and the flsr bit. to put the flash memory back in read mode from the locked state, use the read/reset command to reset the flash memory or a hardware reset to reset the whole chip. in case of a programming failure, it is recommended to replace the chip or discontinue the use of the flash block including this failing address.
tmp92fd54ai 2009-12-26 92fd54ai-53 tentative 5) auto chip erase command the auto chip erase operation will commence after completion of the sixth bus write cycle. the embedded auto chip erase algorithm automatically preprograms the entire memory for all-0 data pattern prior to the erase; then it automatically erases and verifies the entire memory. the auto chip erase algorithm erases the unprotected blocks and ignores the protected blocks. if all the blocks are protected, the auto chip erase command does nothing; the flash memory returns to read mode after the completion of the sixth bus write cycle of the command sequence. any commands written during the chip erase operation are ignored. the system can determine the status of the chip erase operation by using write status flags or the flsr bit. when the embedded auto chip erase algorith m is complete, the flash memory returns to read mode. if any failure occurs during the erase operation, the flash memory remains locked in embedded operation mode. the system can determine this status by using write status flags and the flsr bit. to put the flash memory back in read mode from the locked state, use the read/reset command to reset the flash memory or a hardware reset to reset the whole chip. in this case, however, the failing block cannot be identified by means of the auto chip erase command. it is recommended to replace the chip or discontinue the use of the failing flash block by identifying the failing block by running the auto block erase command. 6) auto block erase command the auto block erase operation will commence after completion of the sixth bus write cycle of the command sequence. the embedded auto block erase algorithm automatically preprograms the selected block for all-0 data pattern, and then erases and verifies that block. the block protection feature disables erase operations in the block. if th e selected block is protected, the auto block erase algorithm does nothing; flash memory re turns to read mode after the completion of the sixth bus write cycle of the command sequence. any commands written during the block erase operation are ignored. the system can determine the status of the erase operation by using write status flags and the flsr bit. when the embedded auto block erase algorithm is complete, the flash memory automatically returns to read mode. if any failure occurs during the erase operation, the flash memory remains locked in automatic operation mode. the system can determine this status by using write status flags or the flsr bit. to put the flash memory back in read mode from the locked state, use the read/reset command to reset the flash memory or a hardware reset to reset the whole chip. in case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block.
tmp92fd54ai 2009-12-26 92fd54ai-54 tentative table 3.5.2 block erase addresses address range block user boot mode single boot mode size ba0 f80000h - f8ffffh 010000h - 01ffffh 64 kbytes ba1 f90000h - f9ffffh 020000h - 02ffffh 64 kbytes ba2 fa0000h - faffffh 030000h - 03ffffh 64 kbytes ba3 fb0000h - fbffffh 040000h - 04ffffh 64 kbytes ba4 fc0000h - fcffffh 050000h - 05ffffh 64 kbytes ba5 fd0000h - fdffffh 060000h - 06ffffh 64 kbytes ba6 fe0000h - fedfffh 070000h - 07dfffh 56 kbytes ba7 fee000h - ffbfffh 07e000h - 08bfffh 56 kbytes ba8 ffc000h - ffdfffh 08c000h - 08dfffh 8 kbytes ba9 ffe000h - ffffffh 08e000h - 08ffffh 8 kbytes the address of the block to be erased can be any of the addresses within that block with a0 = 0 and a1 = 0. for example, to select ba0 in user boot mode, provide any address with a0 = 0 and a1 = 0 in the rang e between f80000h and f8ffffh. 7) auto block protect command the auto block protection feature disables program and erase operations in any block independently from other blocks. the effects of the program and erase commands on the protected/unprotected blocks are summarized below. table 3.5.3 effects of the program and erase commands on the protected blocks command and protected/unprotected block status operation program command on a protected block no programming operation is performed, and the flash memory automatically returns to read mode. block erase command on a protected block no eras e operation is performed, and the flash memory automatically returns to read mode. chip erase command when all the blocks are protected no erase operation is performed, and the flash memory automatically returns to read mode. chip erase command when any blocks are protected only the unprotected blocks are erased. upon completion, the flash memory automatically returns to read mode. the auto block protect command requires six bus write cycles; the block address and command data are written in the sixth cycle, upon completion of which the block protect operation will commence. the embedded auto block protect algorithm automatically performs block protect operations and verifies that protected blocks. any commands written during the auto block protect algorithm are ignored. the system can determine the state of the auto block protect operation by using write status flags or the flsr bit. if any failure occurs during the protect operation, the flash memory remains locked in automatic operation mode. the system can determine this status by using write status flags or the flsr bit. 8) verify block protect command the verify block protect command is used to verify the protect status of a block. the address of the block to be verified is given in the fourth read cycle. any address within the block range will suffice, provided a0 = a1 = a2 = a3 = 0, a4 = 1 and a6 = 0. a longword (32-bit) read should be performed on that address. if the selected block is protected, a value
tmp92fd54ai 2009-12-26 92fd54ai-55 tentative of 0000_0001h is returned. if the selected block is not protected, a value of 0000_0000h is returned. additional blocks may be verified by repeat ing the fourth bus read cycle of the command sequence. longword reads should be performed on addresses within the range of desired blocks. the verify block protect command does not return the flash memory to read mode. either the read/reset command or a hardware reset is required to reset the flash memory to read mode or to write the next command sequence. 9) hardware sequence flags (refer to table 3.5.6) the flash memory provides several flag bits to determine the status of an automatic operation. these status bits can be read du ring an automatic operation using the same timing as for read mode. the flash memory au tomatically returns to read mode when an automatic operation completes. during the automatic program operation, the system must provide the program address (with a0 = 0 and a1 = 0) to read valid status information. z dq7 (data polling) the data polling bit, dq7, indicates the status of the automatic operation. data polling is valid after the final bus write cycle of an automatic command sequence. when the embedded auto program algorithm is in progress, an attempt to read the flash memory will produce the complement (inverted) data last written to dq7. upon completion of the embedded auto program algorithm, an attempt to read will produce the true (non-inverted) data. therefore, the system can use dq7 to determine whether the embedded auto program algorithm is in progress or complete. when the embedded auto erase algorithm is in progress, an attempt to read the flash memory will produce a 0 at the dq7 output. upon completion of the embedded auto erase algorithm, the flash memory will produce a 1 at the dq7 output. if there is a failure during an automatic operation, dq7 continues to output the same value. thus, dq7 must always be polled in conjunction with the exceeded timing limits (dq5 ) flag. (see figure 3.5.9). the flash memory disables address latching when an automatic operation is complete. data polling must be performed with a valid programmed address or an address within any of the non-protected blocks selected for erasure. the system cannot properly determine the status of the auto block protect operation by using the dq7 bit. the togg le bit and the flsr bit must be checked to determine the correct status. z dq6 (toggle bit) basically same as the data polling bit, th e toggle bit, dq6, indicates the status of the automatic operation. toggle bit is valid after the final bus write cycle of an automatic command sequence. every time the flash memory is read while the automatic program algorithm is in prog ress, the dq6 output toggles between 1 and 0. if there is a failure during an automatic operation, dq6 continues to output the same value. thus, dq6 must be used in conjunction with the exceeded timing limits (dq5) flag. (see figure 3.5.10) z dq5 (exceeded timing limits) dq5 produces a 0 while the program or erase operation is in progress normally.
tmp92fd54ai 2009-12-26 92fd54ai-56 tentative dq5 produces a 1 to indicate that the program or erase time has exceeded the specified internal limit. this is a failure condition that indicates the automatic operation is not successfully completed, including the possibility of flash memory failure. a bit in the flash memory cells ca n be programmed from a 1 to a 0, but not vice versa. thus, if the system tries to program a 1 to a location that was previously programmed to a 0, the oper ation cannot be completed within the specified timing limits and dq5 will indicate a 1. note that this is not a device failure condition but the flash memory was used incorrectly. z dq3 (block erase timer) when the erase operation begins, dq3 switches from a 0 to a 1. when the other operations are in progress (such as the au to program operation), the flash memory produces a 0 at the dq3 output. if there is a failure during the auto erase operation, dq3 remains 1. table 3.5.4 hardware sequence flags status d7 (dq7) d6 (dq6) d5 (dq5) d3 (dq3) auto program dq7 toggles 0 0 auto erase 0 toggles 0 1 auto block protect note 2 toggles 0 0 automatic operation in progress auto chip erase & unprotect 0 toggles 0 1 auto program dq7 toggles 1 0 auto erase 0 toggles 1 1 auto block protect note 2 toggles 1 0 time-out in automatic operation (failure) auto chip erase & unprotect 0 toggles 1 1 operation complete read cell data cell data cell data cell data note 1: d31-d8, d4 and d2-d0 are don?t-cares. note 2: the automatic operation status cannot be determined with the data polling bit, dq7. 10) status register this is an 8-bit register that indicates the ready/busy status of an automatic operation algorithm. 7 6 5 4 3 2 1 0 bit symbol - - - - - r/bsy - - read/write r/w r/w r/w r/w r after reset 0 0 0 0 - 1 - - flsr (16eh) function must be written as 0. must be written as 0. must be written as 0. must be written as 0. ready/busy 0: automatic operation algorithm is in progress. 1: automatic operation algorithm is complete. figure 3.5.3 flash status register
tmp92fd54ai 2009-12-26 92fd54ai-57 tentative ? bit 2: r/bsy flag bit the flash memory provides the r/bsy flag bit. the cpu monitors this bit to determine whether an automatic algorithm is in progress or complete. the r/bsy bit is cleared to a 0 when the flash memo ry is actively erasing or programming. the r/bsy bit is set to a 1 when an automatic operation has completed and the flash memory is ready to accept the next command. if any failure occurs during the program or erase operation, this bit rema ins cleared. a hardware reset sets this bit. the r/bsy bit is cleared upon completion of the final bus write cycle of an automatic operation command. any command is ignored while the r/bsy bit is cleared. 11) flash security enable register this is an 8-bit register to enable or disable the auto chip erase & unprotect operation. 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 fswe (16bh) function c9h: auto chip erase & unprotect operation is enabled. other: auto chip erase & unpr otect operation is disabled. figure 3.5.4 flash security enable register the fswe register can only be written by executing the auto program algorithm out of the on-chip ram or an ex ternal memory device. 12) auto chip erase & unprotect command the fswe register must be set to c9h to start the auto chip erase & unprotect operation after the completion of the sixth bus write cycle of the command sequence. the auto chip erase & unprotect algorithm automatically unprotects all the flash blocks, erases the entire flash array, then verifies if the entire flash memory is cleared. any commands written during the chip erase operation are ignored. if the auto chip erase & unprotect operation is successfully completed, the flash memory automatically returns to read mode. the fswe register must be cleared (or programmed to any value other than c9h) if any on-board operation is subsequently required. if any failure occurs during the auto chip erase & unprotect operation, the flash memory remains locked in automatic operati on mode. the system can determine this status by using hardware sequence flags or the fl sr bit.. to put the flash memory back in read mode , use the read/reset command to reset the flash memory or a hardware reset to reset the wh ole chip. in this case, however, there is no way to identify a failing flash block. it is recommended to replace the chip or discontinue the use of the failing flash block by identifying the failing block by means of the block erase command.
tmp92fd54ai 2009-12-26 92fd54ai-58 tentative 13) command sequences the command sequences and addresses for on-board programming are shown in the following tables. table 3.5.5 on-board programming mode command sequences 1st cycle (write) 2nd cycle (write) 3rd cycle (write) 4th cycle (read/write) 5th cycle (read/write) 6th cycle (read/write) command sequence cycles required addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxx00h f0h read/reset 3 xaaa8h aah x5554h 55h xaaa8h f0h ra rd auto program 4 xaaa8h aah x5554h 55h xaaa8h a0h pa pd auto chip erase 6 xaaa8h aah x5554h 55h xaaa8h 80h xaaa8h aah x5554h 55h xaaa8h 10h auto block erase 6 xaaa8h aah x5554h 55h xaaa8h 80h xaaa8h aah x5554h 55h ba 30h block protect 6 xaaa8h aah x5554h 55h xaaa8h 9ah xaaa8h aah x5554h 55h ba 70h verify block protect 4 xaaa8h aah x5554h 55h xaaa8h 90h bpa bd auto chip erase& unprotect (note 1) 6 xaaa8h aah x5554h 55h xaaa8h 80h x aaa8h aah x5554h 55h xaaa8h 10h note 1: the fswe register must be programmed to c9 h before executing the auto chip erase & unprotect command sequence. note 2: there must be an interval of at l east two instructions between each bus cycle. table 3.5.6 addresse s provided by the cpu command address cpu addresses: a23-a0 address a23-a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 xxxxxh x x x x x0000h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xaaa8h 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 x5554h flash memory block 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 ? aah, 55h, f0h, a0h, 10h, 30h, 70h, 80h, 90h, 9ah command data. write command data as a byte quantity. ? ra: read address rd: read data ? pa: program address pd: program data the address must be a multiple of four. write data on a word-by-word basis. ? ba: block address (ba0-ba9) refer to table 3.5.2, block erase addresses. ? bpa: verify block protect address the address of the block to be verified can be any of the addresses within the block, with a6 = 0, a4 = 1, a3 = 0 and a2 = a1 = a0 = 0. ? bd: block protect data if a block is protected, a value of 0000_0001h will be returned. if a block is not protected, a value of 0000_0000h will be returned.
tmp92fd54ai 2009-12-26 92fd54ai-59 tentative 14) automatic operation algorithms figure 3.5.5 shows a flowchart of the auto program operation. for details on the step ?determine the status of an automatic operation,? see figure 3.5.9, data polling (dq7) algorithm, figure 3.5.10, toggle bit (dq6) algorithm, and figure 3.5.11, r/bsy flag algorithm. figure 3.5.5 auto program operation auto program command sequence (shown below) last address ? start no determine the status of an automatic operation (see figure 3.5.9 through figure 3.5.11) yes auto program done address = address + 4 (in longword quantities) auto program command sequence (address/data) xaaa8h / aah x5554h / 55h xaaa8h / a0h program address (a1 = a0 = 0) / program data (in longword quantities)
tmp92fd54ai 2009-12-26 92fd54ai-60 tentative figure 3.5.6 shows flowcharts of the auto chip erase and auto block erase operations. operation flows of these algorithms are the same except the command sequences. for details on the step ?determine the status of an automatic operation,? see figure 3.5.9, data polling (dq7) algorithm, figure 3.5.10, to ggle bit (dq6) algorithm, and figure 3.5.11, r/bsy flag algorithm. figure 3.5.6 auto erase operations auto erase command sequence (shown below) start determine the status of an automatic operation (see figure 3.5.9 through figure 3.5.11) auto erase done auto chip erase command sequence (address/data) xaaa8h / aah x5554h / 55h xaaa8h / 80h xaaa8h / aah x5554h / 55h xaaa8h / 10h auto block erase command sequence (address/data) xaaa8h / aah x5554h / 55h xaaa8h / 80h xaaa8h / aah x5554h / 55h block address / 30h
tmp92fd54ai 2009-12-26 92fd54ai-61 tentative figure 3.5.7 shows a flowchart of the auto block protect operation. for details on the step ?determine the status of an automatic oper ation,? see figure 3.5.10, toggle bit (dq6) algorithm, and figure 3.5.11, r/bsy flag algorithm. figure 3.5.7 auto block protect operation xaaa8h /aah x5554h / 55h xaaa8h / 9ah xaaa8h / aah x5554h / 55h block address / 70h auto block protect done auto block protect command sequence (shown below) start determine the status of an automatic operation (see figure 3.5.10 and figure 3.5.11) auto block protect done auto block protect command sequence (address/data)
tmp92fd54ai 2009-12-26 92fd54ai-62 tentative figure 3.5.8 shows a flowchart of the auto chip protect & unprotect operation. for details on the step ?determine the status of an automatic operation,? see figure 3.5.9, data polling (dq7) algorithm, figure 3.5.10, togg le bit (dq6) algorithm, and figure 3.5.11, r/bsy flag algorithm. figure 3.5.8 auto chip er ase & unprotect operation determine the status of an automatic operation (see figure 3.5.9 through figure 3.5.11) auto chip erase & unprotect command sequence (shown below) auto chip erase & unprotect done fswe (16bh) = 0 fswe (16bh) = c9h start xaaa8h / aah x5554h / 55h xaaa8h / 80h xaaa8h / aah auto chip erase & unprotect command sequence x5554h / 55h xaaa8h / 10h
tmp92fd54ai 2009-12-26 92fd54ai-63 tentative figure 3.5.9 shows a flowchart example of ho w to determine the status of an automatic operation by using the da ta polling (dq7) bit. in the auto block protect operation, its operation status cannot be determined by the data polling (dq7) bit. the toggle (dq6) and r/bsy flag bits should be checked to determine the correct status. note: dq5 will produce a 1 if the system tries to overwrite the progr ammed memory locations. this indicates an incorrect usage of the flash memory, not a device failure. figure 3.5.9 data polling (dq7) algorithm read a longword address = va dq5 = 0 ? start no dq7 = data ? read a longword address = va no dq7 = data ? fail pass yes yes yes no va: addresses of the memory locations being programmed in the auto program operation addresses of the flash memory locations bei ng erased in the auto chip erase operation addresses of the memory locations in the selected block being erased in the auto block erase operation
tmp92fd54ai 2009-12-26 92fd54ai-64 tentative figure 3.5.10 shows a flowchart example of how to determine the status of an automatic operation by using the toggle (dq6) bit. note: dq5 will produce a 1 if the system tries to overwrite the progr ammed memory locations. this indicates an incorrect usage of the flash memory, not a device failure. figure 3.5.10 toggle bit (dq6) algorithm read a longword address = va dq5 = 0 ? no dq6 = toggle? read a longword address = va (2 times) yes dq6 = toggle? fail pass no no yes yes va: addresses of the memory locations being programmed in the auto program operation addresses of the flash memory locations bei ng erased in the auto chip erase operation addresses of the memory locations in the selected block being erased in the auto block erase operation read a longword address = va start
tmp92fd54ai 2009-12-26 92fd54ai-65 tentative figure 3.5.11 shows a flowchart of how to dete rmine the status of an automatic operation by using the r/bsy flag (flsr). note: dq5 will produce a 1 if the system tries to overwrite the progr ammed memory locations. this indicates an incorrect usage of the flash memory, not a device failure. figure 3.5.11 r/bsy flag algorithm read flsr register dq5 = 0 ? flsr = 1 ? no yes yes read a longword address = va start no read flsr register flsr = 1 ? fail pass yes no va: addresses of the memory locations being programmed in the auto program operation addresses of the flash memory locations bei ng erased in the auto chip erase operation addresses of the memory locations in the selected block being erased in the auto block erase operation
tmp92fd54ai 2009-12-26 92fd54ai-66 tentative 4. electrical characteristics 4.1 absolute maximum ratings the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. the equipment manufacturer should design so that no maximum rating value is exceeded. parameter symbol rating unit supply voltage v cc5 ? 0.5 - 6.0 v input voltage v in ? 0.5 - v cc5 + 0.5 v output current (total) iol 100 ma output current (total) ioh ? 100 ma power dissipation (ta = 85 c) p d 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 65 - 150 c operating temperature ? 40 - 85 c operating temperature (during flash program/erase) t opr 0 - 70 c program/erase cycles n ew 100 cycle solderability of lead-free products te s t parameter test condition note use of sn-37pb solder bath solder bath temperature =230 c, dipping time = 5 seconds the number of times = one, use of r-type flux solderability use of sn-3.0ag-0.5cu solder bath solder bath temperature =245 c, dipping time = 5 seconds the number of times = one, use of r-type flux pass: solderability rate until forming 95%
tmp92fd54ai 2009-12-26 92fd54ai-67 tentative 4.2 dc electrical characteristics vcc5 = 4.5 to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min max unit supply voltage v cc5 4.5 5.25 v low-level input voltage p00 - p07 (d0 to d7) pg0 - pg7 pl0 - pl3 v il0 ? 0.3 0.8 v low- level input voltage p00 - p07 (port) p40 - p47 v il1 ? 0.3 0.3 ? vcc5 v low-level input voltage int0 nmi reset p70, p71, p73 - p75 pc0 - pc5 pd0 - pd7 pf0 - pf7 pm0 - pm4 v il2 ? 0.3 0.25 ? vcc5 v p72, pn0 - pn6 v il6 ? 0.3 0.3 ? vcc5 v low-level input voltage am0 - am1 test0 - test1 v il3 ? 0.3 0.3 v low- level input voltage x1, xt1 (crystal) v il4 * vcc3 = 3.3 v ? 0.3 0.2 ? vcc3 v low-level input voltage xt1 (cr) v il5cr * vcc3 = 3.3 v ? 0.3 0.2 ? vcc3 v high-level input voltage p00 - p07 (d0 to d7) pg0 - pg7 pl0 - pl3 v ih0 2.2 vcc5 + 0.3 v high-level input voltage p00 - p07 p40 - p47 v ih1 0.7 ? vcc5 vcc5 + 0.3 v high-level input voltage int0 nmi reset p70, p71, p73 - p75 pc0 - pc5 pd0 - pd7 pf0 - pf7 pm0 - pm4 v ih2 0.75 ? vcc5 vcc5 + 0.3 v p72, pn0 - pn6 v ih6 0.7 ? vcc5 vcc5 + 0.3 v high-level input voltage am0 - am1 test0 - test1 v ih3 vcc5 ? 0.3 vcc5 + 0.3 v high-level input voltage x1, xt1 (crystal) v ih4 * vcc3 = 3.3 v 0.8 ? vcc3 vcc3 + 0.3 v high-level input voltage xt1 (cr) v ih5cr * vcc3 = 3.3 v 0.7 ? vcc3 vcc3 + 0.3 v
tmp92fd54ai 2009-12-26 92fd54ai-68 tentative vcc5 = 4.5 to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min max unit low-level output voltage v ol i ol = 3.0 ma 0.4 v v oh0 i oh = -400 a 2.4 v oh1 i oh = -100 a 0.75*vcc5 v oh2 i oh = -20 a 0.9*vcc5 high-level output voltage v ohn i oh = -200 a , pf6(tx) pin only 0.82*vcc5 v input leakage current i li 0.0 Q vin Q vcc5, vin: input voltage 0.02 (typ.) 5 a output leakage current i lo 0.2 Q vin Q vcc5-0.2, vin: input voltage 0.05 (typ.) 10 a operating current (single chip) (note 1) i cc5 v cc5 = 5.25 v, x1 = 10 mhz (fc = 20 mhz) 80(typ.) 100 ma i cc5idle2 idle2 mode v cc5 = 5.25 v, x1 = 10 mhz (fc = 20 mhz) 90 i cc5idle1 idle1 mode v cc5 = 5.25 v, x1 = 10 mhz (fc = 20 mhz) 30 ma i cc5idle3 idle3 mode v cc5 = 5.25 v, ta = -40 to 85 c v cc5 = 5.25 v, ta = -10 to 55 c 220 140 a operating current (standby) (note 2) i cc5stop stop mode v cc5 = 5.25 v, ta = -40 to 85 c v cc5 = 5.25 v, ta = -10 to 55 c 200 120 a standby voltage (the voltage required to maintain the status of internal storage element, such as registers and ram.) v stb5 v cc3 < v cc5 , v ih1 < v cc5 , v ih2 < v cc5 , v ih3 < v cc5 3.0 5.25 v r rst reset r clk clk pull-up resistor r regen regen 60 220 k ? schmitt trigger hysteresis v th int0, nmi , reset , p70 - p75, pc0 - pc5, pd0 - pd7, pf0 - pf7, pm0 - pm4, pn0 - pn6 0.4 1.0 (typ.) v note 1: value when the external bus is not operating note 2: the i cc5idle3 and i cc5stop values are those measured when the supply voltage sensing circuitry of the ram controller is not operating. single boot mode vcc5 = 4.5 to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c (ta = 0 to 70 c for program/erase operations) parameter symbol conditions min max unit operating current (read) i ddo1 80 100 ma operating current (program) i ddo2 D 100 ma operating current (erase) i ddo3 fc = 20 mhz D 110 ma standby current i dds v cc5 = 5.25 v, ta = -40 to 85 c v cc5 = 5.25 v, ta = -10 to 55 c D 200 120 a
tmp92fd54ai 2009-12-26 92fd54ai-69 tentative 4.3 ac electrical characteristics vcc5 = 4.5 to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c no. parameter symbol min max 20mhz 16mhz unit 1 oscillator frequency (x1/x2) t osc 100 125 100 125 ns 2 system clock cycle period (= t) t cyc 50 62.5 50 62.5 ns 3 clk pulse width low t cl 0.5 t ? 15 10 16 ns 4 clk pulse width high t ch 0.5 t ? 15 10 16 ns 5-1 a0-a23 transition to d0-d7 data in @ 0 wait state t ad 2.0 t ? 50 50 75 ns 5-2 a0-a23 transition to d0-d7 data in @ 1 wait state t ad3 3.0 t ? 50 100 138 ns 6-1 rd asserted to d0-d7 data in @ 0 wait state t rd 1.5 t ? 45 30 49 ns 6-2 rd asserted to d0-d7 data in @ 1 wait state t rd3 2.5 t ? 45 80 111 ns 7-1 rd pulse width low @ 0 wait state t rr 1.5 t ? 20 55 74 ns 7-2 rd pulse width low @ 1 wait state t rr3 2.5 t ? 20 105 136 ns 8 a0-a23 valid to rd asserted t ar 0.5 t ? 20 5 11 ns 9 rd asserted to clk low t rk 0.5 t ? 20 5 11 ns 10 a0-a23 transition to d0-d7 hold t ha 0 0 0 ns 11 rd negated to d0-d7 hold t hr 0 0 0 ns 12 wait setup time t tk 15 15 15 ns 13 wait hold time t kt 5 5 5 ns vcc5 = 4.5 to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c no. parameter symbol min max 20mhz 16mhz unit 1 oscillator frequency (x1/x2) t osc 100 125 100 125 ns 2 system clock cycle period t cyc 50 62.5 50 62.5 ns 3 clk pulse width low t cl 0.5 t ? 15 10 16 ns 4 clk pulse width high t ch 0.5 t ? 15 10 16 ns 5-1 d0-d7 valid to wr negated @ 0 wait state t dw 1.25 t ? 35 28 43 ns 5-2 d0-d7 valid to wr negated @ 1 wait state t dw3 2.25 t ? 35 78 106 ns 6-1 wr pulse width low @ 0 wait state t ww 1.25 t ? 30 33 48 ns 6-2 wr pulse width low @ 1 wait state t ww3 2.25 t ? 30 83 111 ns 7 a0-a23 transition to wr asserted t aw 0.5 t ? 20 5 11 ns 8 wr asserted to clk low t wk 0.5 t ? 20 5 11 ns 9 wr negated to a0-a23 hold t wa 0.25 t ? 5 8 11 ns 10 wr negated to d0-d7 hold t wd 0.25 t ? 5 8 11 ns 11 wait setup time t tk 15 15 15 ns 12 wait hold time t kt 5 5 5 ns 13 rd negated to d0-d7 out t rdo 1.25 t ? 35 20 26 ns ac test conditions: output conditions of the d0 to d7, a0 to a7, a8 to a15, a16 to a23, rd and wr pins: high = 2.0 v, low = 0.8 v, cl = 50 pf output conditions of pins other than the above-mentioned ones: high = 2.0 v, low = 0.8 v, cl = 50 pf input conditions of the p00 to p07 (d0 ? d7) pins: high = 2.4 v, low = 0.45 v, cl = 50 pf input conditions of pins other than the above-mentioned ones: high = 0.8 v cc5 , low = 0.2 v cc5 , cl = 50 pf read c y cle write c y cle
tmp92fd54ai 2009-12-26 92fd54ai-70 tentative (1) read cycle timing (0 wait state) note: the signals other than the x1 signal are derived from the x1 signal. thus, certain timing delays occur in the generation of these signals. since these delay times vary depending on each sample device, the phase differences between the x1 si gnal and the other signals cannot be specified. the phase relationship shown in the above timing diagram is only an example. t ar t ha t osc t cl t ch t cyc t tk t kt t ad t hr t rk x1 inpu t clk outpu t (when clk = fc) wait input a0-a23 outputs cs output rd output data in t rd t rr d0-d7 inputs
tmp92fd54ai 2009-12-26 92fd54ai-71 tentative (2) write cycle timing (0 wait state) note: the signals other than the x1 signal are derived from the x1 signal. thus, certain timing delays occur in the generation of these signals. since these delay times vary depending on each sample device, the phase differences between the x1 si gnal and the other signals cannot be specified. the phase relationship shown in the above timing diagram is only an example. t osc t cl t ch t cyc t tk t kt x1 input clk output (when clk = fc) wait input a0-a23 outputs cs output t wd t dw data out t ww t aw t wk t wa wr output rd output t rdo d0-d7 outputs
tmp92fd54ai 2009-12-26 92fd54ai-72 tentative (3) read cycle timing (1 wait state) (4) write cycle timing (1 wait state) clk output (when clk=fc) wait input a0-a23 outputs cs output rd output wr output d0-d7 outputs t dw3 data out t rdo t tk t kt t tk t kt t ww3 t rr3 t ad3 clk output (when clk=fc) wait input a0-a23 outputs cs output rd output d0-d7 inputs t rd3 data in t tk t kt t tk t kt
tmp92fd54ai 2009-12-26 92fd54ai-73 tentative 4.4 ad converter characteristics vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol min typ. max unit analog reference voltage ( + ) v refh v cc5 ? 0.2 v cc5 v cc5 analog reference voltage ( ? ) v refl gnd gnd gnd supply voltage for ad converter av cc v cc5 ? 0.2 v cc5 v cc5 ground for ad converter av ss gnd gnd gnd analog input voltage av in v refl v refh v supply current for analog reference voltage = 1 0.8 1.2 ma supply current for analog reference voltage = 0 i ref 0.02 5 a total error (excluding quantization error) e t 3.0 lsb note: a least significant bit (lsb) is a unit of voltage equal to the smallest resolution of the ad converter. 3 lsb = 3 (v refh ? v refl )/1024 15mv (v refh = 5.0v, v refl = 0.0v) 4.5 event counters (ti0, ti 4, ti8, ti9, tia, tib) vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz 16 mhz parameter symbol min max min max min max unit clock cycle period t vck 8t + 100 500 600 ns clock pulse width low t vckl 4t + 40 240 290 ns clock pulse width high t vckh 4t + 40 240 290 ns 4.6 serial channel timing (1) sclk input mode (i/o interface mode) vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz 16 mhz parameter symbol min max min max min max unit sclk cycle period t scy 16t 0.8 1.0 s output data to sclk high t oss t scy /2 ? 4t ? 110 90 140 sclk high to output data hold t ohs t scy /2 + 2t 500 625 sclk high to input data hold t hsr 3t+10 160 197.5 sclk high to valid data in t srd t scy 800 1000 ns (2) sclk output mode (i/o interface mode) vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz 16 mhz parameter symbol min max min max min max unit sclk cycle period (programmable) t scy 16t 8192t 0.8 409.6 1.0 512 s output data to sclk high t oss t scy /2 ? 40 360 460 sclk high to output data hold t ohs t scy /2 ? 40 360 460 sclk high to input data hold t hsr 0 0 0 sclk high to valid data in t srd t scy ? t ? 180 570 757.5 ns
tmp92fd54ai 2009-12-26 92fd54ai-74 tentative (3) sclk input mode (uart mode) vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20mhz 16mhz parameter symbol min max min max min max unit sclk cycle period t scy 4t + 20 220 270 sclk pulse width low t scyl 2t + 5 105 130 sclk pulse width high t scyh 2t + 5 105 130 ns 4.7 interrupt operation vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz 16 mhz parameter symbol min max min max min max unit nmi , int0 pulse width low t intal 4t 200 250 nmi , int0 pulse width high t intah 4t 200 250 int1-int7 pulse width low t intbl 8t + 100 500 600 int1-int7 pulse width high t intbh 8t + 100 500 600 ns 1 0 sclk output data txd t hsr valid valid t srd t ohs t scy t oss input data rxd
tmp92fd54ai 2009-12-26 92fd54ai-75 tentative 4.8 serial bus interface vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c fc = 20 mhz 400 khz = 1000 100 khz = 1111 (note2) = 0011 0110 parameter symbol min max min max min max unit scl clock frequency f scl 0 400 0 100 0 fc/(2 n + 8) khz hold time for repeated start condition (after this period, the first clock pulse is generated.) t hd:sta 650 4500 2 n ? 1 /fc low period of the scl clock t low 1300 4700 2 n ? 1 /fc high period of the scl clock t high 600 4000 (2 n ? 1 + 8)/fc setup time for repeated start condition t su:sta software software software data hold time t hd:dat 0 900 0 3450 0 6/fc data setup time t su:dat 100 250 (2 n ? 1 ? 6)/fc data setup time (after transfer 1 st data bit) t su:1stdat 100 250 (2 n ? 1 ? 12)/fc rise time of both sda and scl signals t r 300 (reception) 1000 (reception) fall time of both sda and scl signals t f 300 300 setup time for a stop condition t su:sto 950 4200 (2 n ? 1 + 12)/fc bus free time between a stop and start condition t buf software software software ns capacitive load for each bus line c b 400 400 400 pf noise margin at the low level for each connected device (including hysteresis) v nl 0.2 ? vcc5 0.2 ? vcc5 0.2 ? vcc5 v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ? vcc5 0.2 ? vcc5 0.2 ? vcc5 v pulse width of spikes suppressed by the input filter t sp 0 50 n/a n/a n/a n/a ns note 1: the above values are referred to v ihmin and v ilmax . note 2: value for setting = 0011 - 0110 (n = 8 - 11) includes tf and tr. note 3: n/a = not applicable s: start p: stop sr: restart sda scl t low t f t hd:sta t hd:dat t r t su:dat t f t high t su:sta t hd:sta t sp t su:sto t r t buf s s r p s t su:1stdat
tmp92fd54ai 2009-12-26 92fd54ai-76 tentative 4.9 serial expansion interface vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz parameter symbol min max min max unit seclk cycle period t secyc 5t 40t 250 2000 ns ss asserted to seclk t lead 4t 200 ns seclk to ss negated t lag 4t 200 ns seclk pulse width high t sckh t seclk /2-9 116 ns seclk pulse width low t sckl t seclk /2-9 116 ns input data setup t su t seclk /4-10 52 ns input data hold t h t seclk /4 62 ns output data valid t v t seclk /4 62 ns output data hold t ho 0 0 ns a) sei master (cpha = 0) b) sei master (cpha = 1) t su ss seclk (cpol = 0) seclk (cpol = 1) miso mosi t secyc t h bits 6-1 lsb output bits 6-1 msb output lsb input t v t ho msb input t su bits 6-1 lsb output bits 6-1 msb output ss seclk (cpol = 0) seclk (cpol = 1) miso mosi lsb input t secyc t sckh t sckl t h t v t ho msb input
tmp92fd54ai 2009-12-26 92fd54ai-77 tentative c) sei slave (cpha = 0) d) sei slave (cpha = 1) 4.10 can controller vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c equation 20 mhz symbol parameter min max min max unit tcclk can clock period 2t 100 ns tp tx low/high to rx low/high 2tcclk-20 180 ns t h lsb output bits 6-1 ss seclk (cpol = 0) seclk (cpol = 1) miso mosi msb output t lead t su t v t ho t sckh t lag t sckl bits 6-1 lsb input msb input msb output bits 6-1 lsb output ss seclk (cpol = 0) seclk (cpol = 1) miso mosi t lead t su t v t ho t sckh t lag t h t sckl bits 6-1 lsb input msb input t p tx t p rx
tmp92fd54ai 2009-12-26 92fd54ai-78 tentative 4.11 recommended oscillator circuit recommended oscillator circuits for the tmp92fd54ai are shown below: (1) oscillator circuit examples figure 4.11.1 oscillation circuits note: the load capacitance on the oscillator conn ection pins is the sum of c1 and c2 in the oscillator circuit (or in corporated in a resona tor) and stray board capacitance. since the total load capacitance varies with the board layout, the resonator might fail to work properly. to prevent this problem, the board trac es near the oscillator circuit should be as short as possible. it is recommended to evaluate the oscillato r using the actual application board. (2) recommended ceramic resonator circuit the tmp92fd54ai high-frequency oscillator circuit has been evaluated by murata manufacturing co., ltd. for details, plea se contact your murata representative. figure 4.11.1 shows the recommended circuit constants for the ceramic resonator manufactured by murata. figure 4.11.1 recommended ceramic resonator for the tmp92fd54ai (manufactured by murata) recommended constant tmp92fd54ai operating conditions oscillation frequency [mhz] resonator part number c1 [pf] (note 1) c2 [pf] (note 1) rf [ ? ] rd [ ? ] supply voltage [v] temperature [ c] 8.0 smd cstce8m00g15c() ? r0 (33) (33) open 330 10.0 smd cstce10m0g15c() ? r0 (33) (33) open 330 4.5 to 5.5 ? 40 to 85 note 1: enclosed in parentheses are the built-in load capacitor values. note 2: part numbers and specifications of resona tors manufactured by murata are subject to change without notice. for details, please visit mu rata?s website at http://www.murata.co.jp. x1 x2 c 2 c 1 rd xt1 xt2 c 2 c 1 rd (a) connection with high-frequency oscillator (b) connection with low-frequency oscillator
tmp92fd54ai 2009-12-26 92fd54ai-79 tentative 4.12 voltage regulator voltage regulator vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min typ. max unit input voltage vcc5 including ripple voltage (vp-p). 4.5 5.0 5.25 v ripple frequency 100 hz (sine wave) ? 0 0.75 v ripple frequency > 100 hz (sine wave) ? 0 0.3 v peak-to-peak voltage (ripple voltage) vp-p all ripple frequencies (except sine wave) ? 0 0.2 v output voltage regout 4.5 vin 5.25, iload = 100 ma (vin = vcc5) ta = ? 40 to 85 c 3.0 3.3 3.6 v output current iro vin ? regout = 1.0 v ta = ? 40 to 85 c 0 ? 150 ma iq iload 10 a, ta = ? 40 to 85 c ? ? 80 a iq1 10 a < iload < 100 ma, ta = 25 c ? ? 800 a quiescent current iop iload = 150 ma, ta = ? 40 to 85 c ? ? 10 ma standby current is regen = 0 (regulator only) ? 0.1 0.2 a 0.5 [ ? ] esr 5.0 [ ? ] vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min typ. max unit stabilizing capacitor cs cb = 10 f, esr = 4.7 ? 0.1 ? 10 f bypass capacitor cb cs = 10 f, e s r = 4.7 ? (cs cb) 0.1 ? 10 f input capacitor cin (note) cs = 10 f, e s r = 4.7 ? 4.7 ? 22 f stabilizing resistor esr cs = 10 f, c b = 0.1 f 0.5 ? 5 ? note: tantalum capacitors are recommended. 0.5 [ ? ] esr 50 [ ? ] vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min typ. max unit stabilizing capacitor cs cb = 0.6 f, e s r = 47 ? 0.1 ? 10 f bypass capacitor cb cs = 10 f, e s r = 47 ? (cs cb) 0.6 ? 10 f input capacitor cin (note) cs = 10 f, e s r = 47 ? 4.7 ? 22 f stabilizing resistor esr cs = 10 f, c b = 0.6 f 0.5 ? 50 ? note: tantalum capacitors are recommended. 0.5 [ ? ] esr 100 [ ? ] vcc5 = 4.5 v to 5.25 v / fc = 16 to 20 mhz / ta = ? 40 to 85 c parameter symbol conditions min typ. max unit stabilizing capacitor cs cb = 1.0 f, e s r = 100 ? 0.1 ? 10 f bypass capacitor cb cs = 10 f, e s r = 100 ? (cs cb) 1.0 ? 10 f input capacitor cin (note) cs = 10 f, e s r = 100 ? 4.7 ? 22 f stabilizing resistor esr cs = 10 f, c b = 1.0 f 0.5 ? 100 ? note: tantalum capacitors are recommended. tmp92fd54ai cin regen regout dvcc5 dvss dvcc3 cs esr cb open
tmp92fd54ai 92fd54ai-80 2009-12-26 tentative 5. package dimensions package dimensions lqfp100-p-1414-0.50h 100 ?unit : mm? index 25 26 50 51 75 76 0.08 m s 0.08 s 16.0 0.2 2.0 0.61 14.0 0.1 1.0 0.41 0.1 )( 1.0 () 0.5 0.2 + 0.07 ? 0.03 50.0 1.0 4.1 51.0 + 50.0 ? xam7.1 0 :w:?:?:w8 + 0 . 0 7 5 ? 0 . 0 3 5 0 . 1 2 5 52.0 0.5 () 0.45 :w:?:?:w 0.75 note1: the drawings shown may not accurately represent the actual shape or dimensions.
tmp92fd54ai 92fd54ai-81 2009-12-26 tentative restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively ?toshiba?), re serve the right to make changes to the in formation in this document, and related hardware, software and systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a ma lfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own a pplications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba se miconductor reliability handbook" and (b) the instructions for t he application with which the product will be used with or for. custom ers are solely responsible for all aspects of their own prod uct design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in th is document, or in charts, diagrams, program s, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for suc h designs and applications. toshiba assumes no liability for customers' product design or applications. ? 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